📄 altera_mf.v
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begin
$display("Error: width_result cannot be less than (width_a + width_b)");
$stop;
end
if (width_a <= 0)
begin
$display("Error: width_a must be greater than 0.");
$stop;
end
if (width_b <= 0)
begin
$display("Error: width_b must be greater than 0.");
$stop;
end
if (width_result <= 0)
begin
$display("Error: width_result must be greater than 0.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (input_source_a != "DATAA"))
begin
$display("Error: The input source for port A are limited to input dataa.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (input_source_b != "DATAB"))
begin
$display("Error: The input source for port B are limited to input datab.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_rounding != "NO"))
begin
$display("Error: There is no rounding feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_rounding != "NO"))
begin
$display("Error: There is no rounding feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_saturation != "NO"))
begin
$display("Error: There is no saturation feature for non-StratixII device.");
$stop;
end
if ((dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_saturation != "NO"))
begin
$display("Error: There is no saturation feature for non-StratixII device.");
$stop;
end
temp_sum = 0;
head_result = 0;
head_mult = 0;
overflow_int = 0;
mult_a_reg = 0;
mult_b_reg = 0;
zero_acc_reg = 0;
zero_acc_pipe_reg = 0;
sload_upper_data_reg = 0;
lower_bits = 0;
sload_upper_data_pipe_reg = 0;
sign_a_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
sign_a_pipe_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
sign_b_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
sign_b_pipe_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
addsub_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
addsub_pipe_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
result_int = 0;
result = 0;
overflow = 0;
mult_full = 0;
mult_res_out = 0;
mult_signed_out = 0;
mult_res = 0;
mult_is_saturated_int = 0;
mult_is_saturated_reg = 0;
mult_saturation_tmp = 0;
mult_saturate_overflow = 0;
accum_result = 0;
accum_saturate_overflow = 0;
accum_is_saturated_latent = 0;
for (i=0; i<=extra_accumulator_latency; i=i+1)
begin
result_pipe [i] = 0;
accum_saturate_pipe[i] = 0;
mult_is_saturated_pipe[i] = 0;
end
for (i=0; i<= extra_multiplier_latency; i=i+1)
begin
mult_pipe [i] = 0;
end
end
// ---------------------------------------------------------
// This block updates the internal clock signals accordingly
// every time the global clock signal changes state
// ---------------------------------------------------------
assign input_a_wire_clk = (input_reg_a == "UNREGISTERED")? 0:
(input_reg_a == "CLOCK0")? clock0:
(input_reg_a == "CLOCK1")? clock1:
(input_reg_a == "CLOCK2")? clock2:
(input_reg_a == "CLOCK3")? clock3:0;
assign input_b_wire_clk = (input_reg_b == "UNREGISTERED")? 0:
(input_reg_b == "CLOCK0")? clock0:
(input_reg_b == "CLOCK1")? clock1:
(input_reg_b == "CLOCK2")? clock2:
(input_reg_b == "CLOCK3")? clock3:0;
assign addsub_wire_clk = (addnsub_reg == "UNREGISTERED")? 0:
(addnsub_reg == "CLOCK0")? clock0:
(addnsub_reg == "CLOCK1")? clock1:
(addnsub_reg == "CLOCK2")? clock2:
(addnsub_reg == "CLOCK3")? clock3:0;
assign addsub_pipe_wire_clk = (addnsub_pipeline_reg == "UNREGISTERED")? 0:
(addnsub_pipeline_reg == "CLOCK0")? clock0:
(addnsub_pipeline_reg == "CLOCK1")? clock1:
(addnsub_pipeline_reg == "CLOCK2")? clock2:
(addnsub_pipeline_reg == "CLOCK3")? clock3:0;
assign zero_wire_clk = (accum_sload_reg == "UNREGISTERED")? 0:
(accum_sload_reg == "CLOCK0")? clock0:
(accum_sload_reg == "CLOCK1")? clock1:
(accum_sload_reg == "CLOCK2")? clock2:
(accum_sload_reg == "CLOCK3")? clock3:0;
assign accum_sload_upper_data_wire_clk = (accum_sload_upper_data_reg == "UNREGISTERED")? 0:
(accum_sload_upper_data_reg == "CLOCK0")? clock0:
(accum_sload_upper_data_reg == "CLOCK1")? clock1:
(accum_sload_upper_data_reg == "CLOCK2")? clock2:
(accum_sload_upper_data_reg == "CLOCK3")? clock3:0;
assign zero_pipe_wire_clk = (accum_sload_pipeline_reg == "UNREGISTERED")? 0:
(accum_sload_pipeline_reg == "CLOCK0")? clock0:
(accum_sload_pipeline_reg == "CLOCK1")? clock1:
(accum_sload_pipeline_reg == "CLOCK2")? clock2:
(accum_sload_pipeline_reg == "CLOCK3")? clock3:0;
assign accum_sload_upper_data_pipe_wire_clk = (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 0:
(accum_sload_upper_data_pipeline_reg == "CLOCK0")? clock0:
(accum_sload_upper_data_pipeline_reg == "CLOCK1")? clock1:
(accum_sload_upper_data_pipeline_reg == "CLOCK2")? clock2:
(accum_sload_upper_data_pipeline_reg == "CLOCK3")? clock3:0;
assign sign_a_wire_clk = (sign_reg_a == "UNREGISTERED")? 0:
(sign_reg_a == "CLOCK0")? clock0:
(sign_reg_a == "CLOCK1")? clock1:
(sign_reg_a == "CLOCK2")? clock2:
(sign_reg_a == "CLOCK3")? clock3:0;
assign sign_b_wire_clk = (sign_reg_b == "UNREGISTERED")? 0:
(sign_reg_b == "CLOCK0")? clock0:
(sign_reg_b == "CLOCK1")? clock1:
(sign_reg_b == "CLOCK2")? clock2:
(sign_reg_b == "CLOCK3")? clock3:0;
assign sign_pipe_a_wire_clk = (sign_pipeline_reg_a == "UNREGISTERED")? 0:
(sign_pipeline_reg_a == "CLOCK0")? clock0:
(sign_pipeline_reg_a == "CLOCK1")? clock1:
(sign_pipeline_reg_a == "CLOCK2")? clock2:
(sign_pipeline_reg_a == "CLOCK3")? clock3:0;
assign sign_pipe_b_wire_clk = (sign_pipeline_reg_b == "UNREGISTERED")? 0:
(sign_pipeline_reg_b == "CLOCK0")? clock0:
(sign_pipeline_reg_b == "CLOCK1")? clock1:
(sign_pipeline_reg_b == "CLOCK2")? clock2:
(sign_pipeline_reg_b == "CLOCK3")? clock3:0;
assign multiplier_wire_clk = (multiplier_reg == "UNREGISTERED")? 0:
(multiplier_reg == "CLOCK0")? clock0:
(multiplier_reg == "CLOCK1")? clock1:
(multiplier_reg == "CLOCK2")? clock2:
(multiplier_reg == "CLOCK3")? clock3:0;
assign output_wire_clk = (output_reg == "UNREGISTERED")? 0:
(output_reg == "CLOCK0")? clock0:
(output_reg == "CLOCK1")? clock1:
(output_reg == "CLOCK2")? clock2:
(output_reg == "CLOCK3")? clock3:0;
assign mult_pipe_wire_clk = (multiplier_reg == "UNREGISTERED")? clock0:
multiplier_wire_clk;
assign mult_round_wire_clk = (mult_round_reg == "UNREGISTERED")? 0:
(mult_round_reg == "CLOCK0")? clock0:
(mult_round_reg == "CLOCK1")? clock1:
(mult_round_reg == "CLOCK2")? clock2:
(mult_round_reg == "CLOCK3")? clock3:0;
assign mult_saturation_wire_clk = (mult_saturation_reg == "UNREGISTERED")? 0:
(mult_saturation_reg == "CLOCK0")? clock0:
(mult_saturation_reg == "CLOCK1")? clock1:
(mult_saturation_reg == "CLOCK2")? clock2:
(mult_saturation_reg == "CLOCK3")? clock3:0;
assign accum_round_wire_clk = (accum_round_reg == "UNREGISTERED")? 0:
(accum_round_reg == "CLOCK0")? clock0:
(accum_round_reg == "CLOCK1")? clock1:
(accum_round_reg == "CLOCK2")? clock2:
(accum_round_reg == "CLOCK3")? clock3:0;
assign accum_round_pipe_wire_clk = (accum_round_pipeline_reg == "UNREGISTERED")? 0:
(accum_round_pipeline_reg == "CLOCK0")? clock0:
(accum_round_pipeline_reg == "CLOCK1")? clock1:
(accum_round_pipeline_reg == "CLOCK2")? clock2:
(accum_round_pipeline_reg == "CLOCK3")? clock3:0;
assign accum_saturation_wire_clk = (accum_saturation_reg == "UNREGISTERED")? 0:
(accum_saturation_reg == "CLOCK0")? clock0:
(accum_saturation_reg == "CLOCK1")? clock1:
(accum_saturation_reg == "CLOCK2")? clock2:
(accum_saturation_reg == "CLOCK3")? clock3:0;
assign accum_saturation_pipe_wire_clk = (accum_saturation_pipeline_reg == "UNREGISTERED")? 0:
(accum_saturation_pipeline_reg == "CLOCK0")? clock0:
(accum_saturation_pipeline_reg == "CLOCK1")? clock1:
(accum_saturation_pipeline_reg == "CLOCK2")? clock2:
(accum_saturation_pipeline_reg == "CLOCK3")? clock3:0;
// ----------------------------------------------------------------
// This block updates the internal clock enable signals accordingly
// every time the global clock enable signal changes state
// ----------------------------------------------------------------
assign input_a_wire_en = (input_reg_a == "UNREGISTERED")? 1:
(input_reg_a == "CLOCK0")? ena0:
(input_reg_a == "CLOCK1")? ena1:
(input_reg_a == "CLOCK2")? ena2:
(input_reg_a == "CLOCK3")? ena3:1;
assign input_b_wire_en = (input_reg_b == "UNREGISTERED")? 1:
(input_reg_b == "CLOCK0")? ena0:
(input_reg_b == "CLOCK1")? ena1:
(input_reg_b == "CLOCK2")? ena2:
(input_reg_b == "CLOCK3")? ena3:1;
assign addsub_wire_en = (addnsub_reg == "UNREGISTERED")? 1:
(addnsub_reg == "CLOCK0")? ena0:
(addnsub_reg == "CLOCK1")? ena1:
(addnsub_reg == "CLOCK2")? ena2:
(addnsub_reg == "CLOCK3")? ena3:1;
assign addsub_pipe_wire_en = (addnsub_pipeline_reg == "UNREGISTERED")? 1:
(addnsub_pipeline_reg == "CLOCK0")? ena0:
(addnsub_pipeline_reg == "CLOCK1")? ena1:
(addnsub_pipeline_reg == "CLOCK2")? ena2:
(addnsub_pipeline_reg == "CLOCK3")? ena3:1;
assign zero_wire_en = (accum_sload_reg == "UNREGISTERED")? 1:
(accum_sload_reg == "CLOCK0")? ena0:
(accum_sload_reg == "CLOCK1")? ena1:
(accum_sload_reg == "CLOCK2")? ena2:
(accum_sload_reg == "CLOCK3")? ena3:1;
assign accum_sload_upper_data_wire_en = (accum_sload_upper_data_reg == "UNREGISTERED")? 1:
(accum_sload_upper_data_reg == "CLOCK0")? ena0:
(accum_sload_upper_data_reg == "CLOCK1")? ena1:
(accum_sload_upper_data_reg == "CLOCK2")? ena2:
(accum_sload_upper_data_reg == "CLOCK3")? ena3:1;
assign zero_pipe_wire_en = (accum_sload_pipeline_reg == "UNREGISTERED")? 1:
(accum_sload_pipeline_reg == "CLOCK0")? ena0:
(accum_sload_pipeline_reg == "CLOCK1")? ena1:
(accum_sload_pipeline_reg == "CLOCK2")? ena2:
(accum_sload_pipeline_reg == "CLOCK3")? ena3:1;
assign accum_sload_upper_data_pipe_wire_en = (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 1:
(accum_sload_upper_data_pipeline_reg == "CLOCK0")? ena0:
(accum_sload_upper_data_pipeline_reg == "CLOCK1")? ena1:
(accum_sload_upper_data_pipeline_reg == "CLOCK2")? ena2:
(accum_sload_upper_data_pipeline_reg == "CLOCK3")? ena3:1;
assign sign_a_wire_en = (sign_reg_a == "UNREGISTERED")? 1:
(sign_reg_a == "CLOCK0")? ena0:
(sign_reg_a == "CLOCK1")? ena1:
(sign_reg_a == "CLOCK2")? ena2:
(sign_reg_a == "CLOCK3")? ena3:1;
assign sign_b_wire_en = (sign_reg_b == "UNREGISTERED")? 1:
(sign_reg_b == "CLOCK0")? ena0:
(sign_reg_b == "CLOCK1")? ena1:
(sign_reg_b == "CLOCK2")? ena2:
(sign_reg_b == "CLOCK3")? ena3:1;
assign sign_pipe_a_wire_en = (sign_pipeline_reg_a == "UNREGISTERED")? 1:
(sign_pipeline_reg_a == "CLOCK0")? ena0:
(sign_pipeline_reg_a == "CLOCK1")? ena1:
(sign_pipeline_reg_a == "CLOCK2")? ena2:
(sign_pipeline_reg_a == "CLOCK3")? ena3:1;
assign sign_pipe_b_wire_en = (sign_pipeline_reg_b == "UNREGISTERED")? 1:
(sign_pipeline_reg_b == "CLOCK0")? ena0:
(sign_pipeline_reg_b == "CLOCK1")? ena1:
(sign_pipeline_reg_b == "CLOCK2")? ena2:
(sign_pipeline_reg_b == "CLOCK3")? ena3:1;
assign multiplier_wire_en = (multiplier_reg == "UNREGISTERED")? 1:
(multiplier_reg == "CLOCK0")? ena0:
(multiplier_reg == "CLOCK1")? ena1:
(multiplier_reg == "CLOCK2")? ena2:
(multiplier_reg == "CLOCK3")? ena3:1;
assign output_wire_en = (output_reg == "UNREGISTERED")? 1:
(output_reg == "CLOCK0")? ena0:
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