altera_mf.v

SDRAM 控制器

    input aclr1;
    input aclr2;
    input aclr3;

    // round and saturate ports
    input mult_round;
    input mult_saturation;
    input accum_round;
    input accum_saturation;

    // output ports
    output [width_result -1 : 0] result;
    output overflow;
    output [width_a -1 : 0] scanouta;
    output [width_b -1 : 0] scanoutb;

    output mult_is_saturated;
    output accum_is_saturated;


    // ---------------
    // REG DECLARATION
    // ---------------
    reg [width_result -1 : 0] result;
    reg [width_result -1 + 4 : 0] mult_res_out;
    reg [width_result + 4 : 0] temp_sum;

    reg [width_result + 1 : 0] result_pipe [extra_accumulator_latency : 0];
    reg [width_result + 1 : 0] result_full ;
    reg [width_result - 1 + 4 : 0] result_int;
        
    reg [width_a - 1 : 0] mult_a_reg;
    reg [width_a - 1 : 0] mult_a_int;
    reg [width_a + width_b - 1 + 4: 0] mult_res;
    reg [width_a + width_b - 1 : 0] temp_mult_1;
    reg [width_a + width_b - 1 : 0] temp_mult;


    reg [width_b -1 :0] mult_b_reg;
    reg [width_b -1 :0] mult_b_int;
    
    reg [4 + width_a + width_b + width_result + 1 + 4 + 4 : 0] mult_pipe [extra_multiplier_latency:0];
    reg [4 + width_a + width_b + width_result + 1 + 4 + 4 : 0] mult_full;
    reg [width_result -1 + 4 : 0] sload_upper_data_reg;

    reg [width_result - width_upper_data -1 + 4 : 0] lower_bits;

    reg mult_signed_out;
    reg [width_result -1 + 4 : 0] sload_upper_data_pipe_reg;


    reg zero_acc_reg;
    reg zero_acc_pipe_reg;
    reg sign_a_reg;
    reg sign_a_pipe_reg;
    reg sign_b_reg;
    reg sign_b_pipe_reg;
    reg addsub_reg;
    reg addsub_pipe_reg;

    reg mult_signed;
    reg temp_mult_signed;
    reg neg_a;
    reg neg_b;

    reg overflow_int;
    reg cout_int;
    reg overflow_tmp_int;

    reg overflow;
    
    reg [width_a + width_b -1 : 0] mult_round_out;
    reg mult_saturate_overflow;
    reg [width_a + width_b -1 + 4 : 0] mult_saturate_out;
    reg [width_a + width_b -1 + 4 : 0] mult_result;
    reg [width_a + width_b -1 + 4 : 0] mult_final_out;

    reg [width_result -1 + 4 : 0] accum_round_out;    
    reg accum_saturate_overflow;
    reg [width_result -1 + 4 : 0] accum_saturate_out;
    reg [width_result -1 + 4 : 0] accum_result;
    reg [width_result -1 + 4 : 0] accum_final_out;

    tri0 mult_is_saturated_latent;
    reg mult_is_saturated_int;
    reg mult_is_saturated_reg;
    
    reg accum_is_saturated_latent;
    reg [extra_accumulator_latency : 0] accum_saturate_pipe;
    reg [extra_accumulator_latency : 0] mult_is_saturated_pipe;
    
    reg  mult_round_tmp;
    reg  mult_saturation_tmp;
    reg  accum_round_tmp1;
    reg  accum_round_tmp2;
    reg  accum_saturation_tmp1;
    reg  accum_saturation_tmp2;
    
    reg  [width_result - width_a - width_b + 2 - 1 : 0] accum_result_sign_bits;

    // -------------------
    // INTEGER DECLARATION
    // -------------------
    integer head_result;
    integer i;
    integer i2;
    integer i3;
    integer head_mult;



    //-----------------
    // TRI DECLARATION
    //-----------------


    // Tri wire for clear signal

    tri0 input_a_wire_clr;
    tri0 input_b_wire_clr;

    tri0 addsub_wire_clr;
    tri0 addsub_pipe_wire_clr;

    tri0 zero_wire_clr;
    tri0 zero_pipe_wire_clr;

    tri0 sign_a_wire_clr;
    tri0 sign_pipe_a_wire_clr;

    tri0 sign_b_wire_clr;
    tri0 sign_pipe_b_wire_clr;

    tri0 multiplier_wire_clr;
    tri0 mult_pipe_wire_clr;

    tri0 output_wire_clr;

    tri0 mult_round_wire_clr;
    tri0 mult_saturation_wire_clr;

    tri0 accum_round_wire_clr;
    tri0 accum_round_pipe_wire_clr;

    tri0 accum_saturation_wire_clr;
    tri0 accum_saturation_pipe_wire_clr;

    tri0 accum_sload_upper_data_wire_clr;
    tri0 accum_sload_upper_data_pipe_wire_clr;

    
    // Tri wire for enable signal

    tri1 input_a_wire_en;
    tri1 input_b_wire_en;

    tri1 addsub_wire_en;
    tri1 addsub_pipe_wire_en;

    tri1 zero_wire_en;
    tri1 zero_pipe_wire_en;

    tri1 sign_a_wire_en;
    tri1 sign_pipe_a_wire_en;

    tri1 sign_b_wire_en;
    tri1 sign_pipe_b_wire_en;

    tri1 multiplier_wire_en;
    tri1 mult_pipe_wire_en; 

    tri1 output_wire_en;

    tri1 mult_round_wire_en;
    tri1 mult_saturation_wire_en;

    tri1 accum_round_wire_en;
    tri1 accum_round_pipe_wire_en;

    tri1 accum_saturation_wire_en;
    tri1 accum_saturation_pipe_wire_en;

    tri1 accum_sload_upper_data_wire_en;
    tri1 accum_sload_upper_data_pipe_wire_en;

    // ------------------------
    // SUPPLY WIRE DECLARATION
    // ------------------------

    supply0 [width_a + width_b-1:0] temp_mult_zero;


    // ----------------
    // WIRE DECLARATION
    // ----------------

    // Wire for Clock signals

    wire input_a_wire_clk;
    wire input_b_wire_clk;

    wire addsub_wire_clk;
    wire addsub_pipe_wire_clk;

    wire zero_wire_clk;
    wire zero_pipe_wire_clk;

    wire sign_a_wire_clk;
    wire sign_pipe_a_wire_clk;

    wire sign_b_wire_clk;
    wire sign_pipe_b_wire_clk;

    wire multiplier_wire_clk;
    wire mult_pipe_wire_clk; 

    wire output_wire_clk;

    wire [width_a -1 : 0] scanouta;
    wire [width_a + width_b -1 + 4 : 0] mult_out_latent;
    wire [width_b -1 : 0] scanoutb;

    wire addsub_int;
    wire sign_a_int;
    wire sign_b_int;

    wire zero_acc_int;
    wire sign_a_reg_int;
    wire sign_b_reg_int;

    wire addsub_latent;
    wire zeroacc_latent;
    wire signa_latent;
    wire signb_latent;
    wire mult_signed_latent;

    wire [width_result -1 + 4 : 0] sload_upper_data_latent;
    wire [width_result -1 + 4 : 0] sload_upper_data_pipe_wire;

    wire [width_a -1 :0] mult_a_wire;
    wire [width_b -1 :0] mult_b_wire;
    wire [width_result -1 + 4 : 0] sload_upper_data_wire;
    wire [width_a -1 : 0] mult_a_tmp;
    wire [width_b -1 : 0] mult_b_tmp;

    wire zero_acc_wire;
    wire zero_acc_pipe_wire;

    wire sign_a_wire;
    wire sign_a_pipe_wire;
    wire sign_b_wire;
    wire sign_b_pipe_wire;

    wire addsub_wire;
    wire addsub_pipe_wire;

    wire mult_round_int;
    wire mult_round_wire_clk;
    wire mult_saturation_int;
    wire mult_saturation_wire_clk;

    wire accum_round_tmp1_wire;
    wire accum_round_wire_clk;
    wire accum_round_int;
    wire accum_round_pipe_wire_clk;
    
    wire accum_saturation_tmp1_wire;
    wire accum_saturation_wire_clk;
    wire accum_saturation_int;
    wire accum_saturation_pipe_wire_clk;

    wire accum_sload_upper_data_wire_clk;
    wire accum_sload_upper_data_pipe_wire_clk;
    wire [width_result -1 : width_result - width_upper_data] accum_sload_upper_data_int;
   
    tri0 mult_is_saturated_wire;
            
    // ------------------------
    // COMPONENT INSTANTIATIONS
    // ------------------------
    ALTERA_DEVICE_FAMILIES dev ();


    // --------------------
    // ASSIGNMENT STATEMENTS
    // --------------------
    assign addsub_int     = ((addnsub ===1'bz) ||
                             (addsub_wire_clk ===1'bz) ||
                             (addsub_pipe_wire_clk===1'bz)) ?
                                 ((accum_direction == "ADD") ? 1: 0) : addsub_pipe_wire;
    assign sign_a_int     = ((signa ===1'bz) ||
                             (sign_a_wire_clk ===1'bz) ||
                             (sign_pipe_a_wire_clk ===1'bz)) ?
                                 ((representation_a == "SIGNED") ? 1 : 0) : sign_a_pipe_wire;
    assign sign_b_int     = ((signb ===1'bz) ||
                             (sign_b_wire_clk ===1'bz) ||
                             (sign_pipe_b_wire_clk ===1'bz)) ?
                                 ((representation_b == "SIGNED") ? 1 : 0) : sign_b_pipe_wire;
    assign sign_a_reg_int = ((signa ===1'bz) ||
                             (sign_a_wire_clk ===1'bz) ||
                             (sign_pipe_a_wire_clk ===1'bz)) ?
                                 ((representation_a == "SIGNED") ? 1 : 0) : sign_a_wire;
    assign sign_b_reg_int = ((signb ===1'bz) ||
                             (sign_b_wire_clk ===1'bz) ||
                             (sign_pipe_b_wire_clk ===1'bz)) ?
                                 ((representation_b == "SIGNED") ? 1 : 0) : sign_b_wire;
    assign zero_acc_int   = ((accum_sload ===1'bz) ||
                             (zero_wire_clk===1'bz) ||
                             (zero_pipe_wire_clk===1'bz)) ?
                                 0 : zero_acc_pipe_wire;
                                 
    assign accum_sload_upper_data_int = ((accum_sload_upper_data === {width_upper_data{1'bz}}) ||
                                         (accum_sload_upper_data_wire_clk === 1'bz) ||
                                         (accum_sload_upper_data_pipe_wire_clk === 1'bz)) ?
                                             {width_upper_data{1'b0}} : accum_sload_upper_data;

    assign scanouta       = mult_a_wire;
    assign scanoutb       = mult_b_wire;
    
    assign {addsub_latent, zeroacc_latent, signa_latent, signb_latent, mult_signed_latent, mult_out_latent, sload_upper_data_latent, mult_is_saturated_latent} = (extra_multiplier_latency > 0) ?
               mult_full : {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow};

    assign mult_is_saturated = (port_mult_is_saturated != "UNUSED") ? mult_is_saturated_int : 0;
    assign accum_is_saturated = (port_accum_is_saturated != "UNUSED") ? accum_is_saturated_latent : 0;    


    // ---------------------------------------------------------------------------------
    // Initialization block where all the internal signals and registers are initialized
    // ---------------------------------------------------------------------------------
    initial
    begin

        // Checking for invalid parameters, in case Wizard is bypassed (hand-modified).
        
        if ((dedicated_multiplier_circuitry != "AUTO") && 
            (dedicated_multiplier_circuitry != "YES") && 
            (dedicated_multiplier_circuitry != "NO"))
        begin
            $display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value.");
            $stop;
        end                
        if (width_result < (width_a + width_b))