altera_mf.v

SDRAM 控制器

// Copyright (C) 1988-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Quartus II 4.0 Build 190 1/28/2004

//START_MODULE_NAME------------------------------------------------------------
//
// Module Name     :  ALTERA_DEVICE_FAMILIES
//
// Description     :  Common Altera device families comparison
//
// Limitation      :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------

`timescale 1 ps / 1 ps
module lcell (in, out);
    input in;
    output out;

    assign out = in;
endmodule

`timescale 1 ps / 1 ps
module global (in, out);
    input in;
    output out;

    assign out = in;
endmodule

`timescale 1 ps / 1 ps
module carry (in, out);
    input in;
    output out;

    assign out = in;
endmodule

`timescale 1 ps / 1 ps
module cascade (in, out);
    input in;
    output out;

    assign out = in;
endmodule

`timescale 1 ps / 1 ps
module carry_sum (sin, cin, sout, cout);
    input sin;
    input cin;
    output sout;
    output cout;

    assign sout = sin;
    assign cout = cin;
endmodule

`timescale 1 ps / 1 ps
module exp (in, out);
    input in;
    output out;

    assign out = ~in;
endmodule

// BEGINNING OF MODULE
`timescale 1 ps / 1 ps

// MODULE DECLARATION
module ALTERA_DEVICE_FAMILIES;

// FUNCTON DECLARATION
function IS_VALID_FAMILY;
    input device;
    reg[8*20:1] device;
    reg is_valid;
begin
    if (IS_FAMILY_APEX20K(device) || IS_FAMILY_APEX20KE(device) ||
    IS_FAMILY_APEXII(device) || IS_FAMILY_ACEX2K(device) || IS_FAMILY_STRATIXGX(
    device) || IS_FAMILY_STRATIX(device) || IS_FAMILY_MERCURY(device) ||
    IS_FAMILY_STRATIXII(device) || IS_FAMILY_MAXII(device))
        is_valid = 1;
    else
        is_valid = 0;

    IS_VALID_FAMILY = is_valid;
end
endfunction // IS_VALID_FAMILY

function IS_FAMILY_APEX20K;
    input device;
    reg[8*20:1] device;
    reg is_20k;
begin
    if (device == "APEX20K")
        is_20k = 1;
    else
        is_20k = 0;

    IS_FAMILY_APEX20K = is_20k;
end
endfunction // IS_FAMILY_APEX20K

function IS_FAMILY_APEX20KE;
    input device;
    reg[8*20:1] device;
    reg is_20ke;
begin
    if ((device == "APEX20KE") || (device == "APEX20KC") ||
    (device == "EXCALIBUR_ARM") || (device == "EXCALIBUR_MIPS"))
        is_20ke = 1;
    else
        is_20ke = 0;

    IS_FAMILY_APEX20KE = is_20ke;
end
endfunction // IS_FAMILY_APEX20KE

function IS_FAMILY_APEXII;
    input device;
    reg[8*20:1] device;
    reg is_apexii;
begin
    if ((device == "APEX II") || (device == "APEXII"))
        is_apexii = 1;
    else
        is_apexii = 0;

    IS_FAMILY_APEXII = is_apexii;
end
endfunction // IS_FAMILY_APEXII

function IS_FAMILY_ACEX2K;
    input device;
    reg[8*20:1] device;
    reg is_acex2k;
begin
    if ((device == "CYCLONE") || (device == "Cyclone"))
        is_acex2k = 1;
    else
        is_acex2k = 0;

    IS_FAMILY_ACEX2K = is_acex2k;
end
endfunction // IS_FAMILY_ACEX2K

function IS_FAMILY_STRATIXGX;
    input device;
    reg[8*20:1] device;
    reg is_stratixgx;
begin
    if ((device == "STRATIX-GX") || (device == "STRATIX GX") ||
    (device == "Stratix GX"))
        is_stratixgx = 1;
    else
        is_stratixgx = 0;

    IS_FAMILY_STRATIXGX = is_stratixgx;
end
endfunction // IS_FAMILY_STRATIXGX

function IS_FAMILY_STRATIX;
    input device;
    reg[8*20:1] device;
    reg is_stratix;
begin
    if ((device == "STRATIX") || (device == "Stratix"))
        is_stratix = 1;
    else
        is_stratix = 0;

    IS_FAMILY_STRATIX = is_stratix;
end
endfunction // IS_FAMILY_STRATIX

function IS_FAMILY_MERCURY;
    input device;
    reg[8*20:1] device;
    reg is_mercury;
begin
    if ((device == "MERCURY") || (device == "Mercury"))
        is_mercury = 1;
    else
        is_mercury = 0;

    IS_FAMILY_MERCURY = is_mercury;
end
endfunction // IS_FAMILY_MERCURY

function IS_FAMILY_FLEX10KE;
    input device;
    reg[8*20:1] device;
    reg is_flex10ke;
begin
    if ((device == "FLEX10KE") || (device == "FLEX 10KE") ||
        (device == "ACEX1K") || (device == "ACEX 1K"))
        is_flex10ke = 1; 
    else 
        is_flex10ke = 0;
    
    IS_FAMILY_FLEX10KE = is_flex10ke;
end
endfunction // IS_FAMILY_FLEX10KE

function IS_FAMILY_STRATIXII;
    input device;
    reg[8*20:1] device;
    reg is_stratixii;
begin
    if ((device == "Stratix II") || (device == "StratixII"))
        is_stratixii = 1; 
    else 
        is_stratixii = 0;
    
    IS_FAMILY_STRATIXII = is_stratixii;
end
endfunction // IS_FAMILY_STRATIXII 

function IS_FAMILY_STRATIXHC;
    input device;
    reg[8*20:1] device;
    reg is_stratixhc;
begin
    if ((device == "STRATIXHC")  || (device == "StratixHC") ||
        (device == "STRATIX HC") || (device == "Stratix HC") ||
        (device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX"))
        is_stratixhc = 1;
    else
        is_stratixhc = 0;

    IS_FAMILY_STRATIXHC = is_stratixhc;
end
endfunction // IS_FAMILY_STRATIXHC

function IS_FAMILY_MAXII;
    input device;
    reg[8*20:1] device;
    reg is_maxii;
begin
    if ((device == "MAX II") || (device == "max ii") ||
        (device == "MAXII") || (device == "maxii"))
        is_maxii = 1;
    else
        is_maxii = 0;

    IS_FAMILY_MAXII  = is_maxii;
end
endfunction //IS_FAMILY_MAXII

endmodule // ALTERA_DEVICE_FAMILIES

//START_MODULE_NAME------------------------------------------------------------
//
// Module Name     :  altaccumulate
//
// Description     :  Parameterized accumulator megafunction. The accumulator
// performs an add function or a subtract function based on the add_sub
// parameter. The input data can be signed or unsigned.
//
// Limitation      : n/a
//
// Results expected:  result - The results of add or subtract operation. Output
//                             port [width_out-1 .. 0] wide.
//                    cout   - The cout port has a physical interpretation as 
//                             the carry-out (borrow-in) of the MSB. The cout
//                             port is most meaningful for detecting overflow
//                             in unsigned operations. The cout port operates
//                             in the same manner for signed and unsigned
//                             operations.
//                    overflow - Indicates the accumulator is overflow.
//
//END_MODULE_NAME--------------------------------------------------------------

// BEGINNING OF MODULE

`timescale 1 ps / 1 ps

module altaccumulate (cin, data, add_sub, clock, sload, clken, sign_data, aclr,
                      result, cout, overflow);

    parameter width_in = 4;     // Required
    parameter width_out = 8;    // Required
    parameter lpm_representation = "UNSIGNED";
    parameter extra_latency = 0;
    parameter use_wys = "ON";
    parameter lpm_hint = "UNUSED";
    parameter lpm_type = "altaccumulate";

    // INPUT PORT DECLARATION
    input cin;
    input [width_in-1:0] data;  // Required port
    input add_sub;              // Default = 1
    input clock;                // Required port
    input sload;                // Default = 0
    input clken;                // Default = 1
    input sign_data;            // Default = 0
    input aclr;                 // Default = 0

    // OUTPUT PORT DECLARATION
    output [width_out-1:0] result;  //Required port
    output cout;
    output overflow;

    // INTERNAL REGISTERS DECLARATION
    reg [width_out:0] temp_sum;
    reg overflow;
    reg overflow_int;
    reg cout_int;
    reg cout_delayed;

    reg [width_out-1:0] result;
    reg [width_out+1:0] result_int;
    reg [(width_out - width_in) : 0] zeropad;

    reg borrow;
    reg cin_int;

    reg [width_out-1:0] fb_int;
    reg [width_out -1:0] data_int;

    reg [width_out+1:0] result_pipe [extra_latency:0];