_primary.vhd

来自「SDRAM 控制器」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity hssi_tx is
    generic(
        channel_width   : integer := 1
    );
    port(
        clk             : in     vl_logic;
        datain          : in     vl_logic_vector;
        areset          : in     vl_logic;
        dataout         : out    vl_logic;
        clkout          : out    vl_logic
    );
end hssi_tx;