cpld_bus.map.rpt

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

;    |Output_reg:inst8|      ; 1          ; 0    ; |cpld_bus|Output_reg:inst8   ;
;    |bus_ISM:inst|          ; 4          ; 0    ; |cpld_bus|bus_ISM:inst       ;
;    |decode:inst5|          ; 4          ; 0    ; |cpld_bus|decode:inst5       ;
+----------------------------+------------+------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/project/cpld_bus/cpld_bus.map.eqn.


+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                  ;
+----------------------------------+-----------------+------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path       ;
+----------------------------------+-----------------+------------------------------------+
; decode.v                         ; yes             ; E:/project/cpld_bus/decode.v       ;
; cpld_bus.bdf                     ; yes             ; E:/project/cpld_bus/cpld_bus.bdf   ;
; bus_ISM.v                        ; yes             ; E:/project/cpld_bus/bus_ISM.v      ;
; data_out_mux.v                   ; yes             ; E:/project/cpld_bus/data_out_mux.v ;
; Output_reg.v                     ; yes             ; E:/project/cpld_bus/Output_reg.v   ;
+----------------------------------+-----------------+------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 76                   ;
; Total registers      ; 8                    ;
; I/O pins             ; 62                   ;
; Parallel expanders   ; 16                   ;
; Maximum fan-out node ; WR_N                 ;
; Maximum fan-out      ; 39                   ;
; Total fan-out        ; 498                  ;
; Average fan-out      ; 3.61                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
    Info: Processing started: Thu Aug 04 20:04:25 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpld_bus -c cpld_bus
Info: Found 1 design units, including 1 entities, in source file decode.v
    Info: Found entity 1: decode
Info: Found 1 design units, including 1 entities, in source file cpld_bus.bdf
    Info: Found entity 1: cpld_bus
Info: Found 1 design units, including 1 entities, in source file bus_ISM.v
    Info: Found entity 1: bus_ISM
Info: Found 1 design units, including 1 entities, in source file data_out_mux.v
    Info: Found entity 1: Data_Out_Mux
Info: Found 1 design units, including 1 entities, in source file Output_reg.v
    Info: Found entity 1: Output_reg
Warning: Can't find a definition for parameter STATUS_REG -- assuming BASE_ADDR+8'b10000000 was intended to be a quoted string
Warning: Can't find a definition for parameter CONTROL_REG -- assuming BASE_ADDR+8'b10000010 was intended to be a quoted string
Warning: Can't find a definition for parameter DATAIN_REG -- assuming BASE_ADDR+8'b10000100 was intended to be a quoted string
Warning: Can't find a definition for parameter DATAOUT_REG -- assuming BASE_ADDR+8'b10000110 was intended to be a quoted string
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Verilog HDL Always Construct warning at data_out_mux.v(19): variable "Data_inA" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at data_out_mux.v(20): variable "Data_inB" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at data_out_mux.v(21): variable "Data_inC" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at data_out_mux.v(22): variable "Data_inD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at decode.v(17): truncated value with size 2 to match size of target (1)
Warning: Verilog HDL Always Construct warning at Output_reg.v(17): variable "addr_data" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at Output_reg.v(12): variable data may not be assigned a new value in every possible path through the Always Construct.  Variable data holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: State machine "|cpld_bus|bus_ISM:inst|state" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|cpld_bus|bus_ISM:inst|state"
Info: Encoding result for state machine "|cpld_bus|bus_ISM:inst|state"
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit "bus_ISM:inst|state~15"
        Info: Encoded state bit "bus_ISM:inst|state~14"
    Info: State "|cpld_bus|bus_ISM:inst|state.idle" uses code string "00"
    Info: State "|cpld_bus|bus_ISM:inst|state.data_trs_state" uses code string "10"
    Info: State "|cpld_bus|bus_ISM:inst|state.ADDR_decode" uses code string "01"
    Info: State "|cpld_bus|bus_ISM:inst|state.end_cycle" uses code string "11"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "Output_reg:inst6|data_out[7]~0" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[7]~0" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[7]~0" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[7]~0" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[6]~1" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[6]~1" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[6]~1" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[6]~1" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[5]~2" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[5]~2" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[5]~2" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[5]~2" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[4]~3" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[4]~3" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[4]~3" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[4]~3" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[3]~4" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[3]~4" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[3]~4" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[3]~4" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[2]~5" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[2]~5" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[2]~5" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[2]~5" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[1]~6" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[1]~6" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[1]~6" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[1]~6" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst6|data_out[0]~7" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst7|data_out[0]~7" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst4|data_out[0]~7" that feeds logic to an OR gate
    Warning: Converting TRI node "Output_reg:inst8|data_out[0]~7" that feeds logic to an OR gate
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clock signal driven by pin "ALE_E" to global clock signal
    Info: Promoted clear signal driven by pin "reset" to global clear signal
Info: Implemented 138 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 40 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 76 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 49 warnings
    Info: Processing ended: Thu Aug 04 20:04:30 2005
    Info: Elapsed time: 00:00:05