cpld_bus.dse.rpt

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

Design Space Explorer Report
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+------------------------------------------------------------------------+
| Report Information                                                     |
+------------------------------------------------------------------------+
+--------------------+-------------------------------------------------+
| Start Date & Time  | 2005年7月29日 16:26:41                          |
| Working Directory  | E:/project/cpld_bus                             |
| Project Name       | cpld_bus                                        |
| Revision Name      | cpld_bus                                        |
| Quartus II Version | Version 4.2 Build 156 11/29/2004 SJ Web Edition |
+--------------------+-------------------------------------------------+

Table of Contents
    Report Information
    Legal Notice
    Flow Messages
    Flow Summary

+-----------------------------------------------------------------------------+
| Legal Notice                                                                |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2004 Altera Corporation. All rights reserved.
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.

+-----------------------------------------------------------------------------+
| Flow Messages                                                               |
+-----------------------------------------------------------------------------+

Info: Loading space: Physical Synthesis with Retiming Space
Info: Loading space: Seeds
Info: Design space contains 8 points

+-----------------------------------------------------------------------------+
| Settings for base                                                           |
+-----------------------------------------------------------------------------+
+-----------------------------------------+----------+
| Setting                                 | Value    |
+-----------------------------------------+----------+
| PHYSICAL_SYNTHESIS_REGISTER_RETIMING    | Off      |
| PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION | Off      |
| AUTO_PACKED_REGISTERS_STRATIX           | AUTO     |
| ADV_NETLIST_OPT_SYNTH_GATE_RETIME       | Off      |
| SEED                                    | 1        |
| PHYSICAL_SYNTHESIS_COMBO_LOGIC          | Off      |
| ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP     | Off      |
| FITTER_EFFORT                           | Auto Fit |
| INNER_NUM                               |          |
| PHYSICAL_SYNTHESIS_EFFORT               | Normal   |
+-----------------------------------------+----------+

Info: Running quartus_map on base
Info: Exploration has finished
Info: (0 warnings, 0 errors)