cpld_bus.tan.qmsg

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

{ "Info" "ITDB_FULL_TPD_RESULT" "WR_N data_out10 22.000 ns Longest " "Info: Longest tpd from source pin \"WR_N\" to destination pin \"data_out10\" is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns WR_N 1 PIN PIN_81 72 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 72; PIN Node = 'WR_N'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { WR_N } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 376 -48 120 392 "WR_N" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns Output_reg:inst6\|always0~35 2 COMB LC8 8 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC8; Fanout = 8; COMB Node = 'Output_reg:inst6\|always0~35'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "9.000 ns" { WR_N Output_reg:inst6|always0~35 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(9.000 ns) 22.000 ns data_out10 3 PIN PIN_51 0 " "Info: 3: + IC(2.000 ns) + CELL(9.000 ns) = 22.000 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'data_out10'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "11.000 ns" { Output_reg:inst6|always0~35 data_out10 } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 248 688 864 264 "data_out1\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns 81.82 % " "Info: Total cell delay = 18.000 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 18.18 % " "Info: Total interconnect delay = 4.000 ns ( 18.18 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "22.000 ns" { WR_N Output_reg:inst6|always0~35 data_out10 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "22.000 ns" { WR_N WR_N~out Output_reg:inst6|always0~35 data_out10 } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 9.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "bus_ISM:inst\|state~14 ALE_E clk -3.000 ns register " "Info: th for register \"bus_ISM:inst\|state~14\" (data pin = \"ALE_E\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { clk } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 360 -48 120 376 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns bus_ISM:inst\|state~14 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "0.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns ALE_E 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { ALE_E } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 328 -48 120 344 "ALE_E" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns bus_ISM:inst\|state~14 2 REG LC9 9 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "7.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "10.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { ALE_E ALE_E~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "10.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { ALE_E ALE_E~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 20:04:40 2005 " "Info: Processing ended: Thu Aug 04 20:04:40 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}