cpld_bus.tan.qmsg

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE_E " "Info: Assuming node \"ALE_E\" is an undefined clock" {  } { { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 328 -48 120 344 "ALE_E" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ALE_E" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 360 -48 120 376 "clk" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE_E " "Info: No valid register-to-register data paths exist for clock \"ALE_E\"" {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register bus_ISM:inst\|state~14 register bus_ISM:inst\|data_oe 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"bus_ISM:inst\|state~14\" and destination register \"bus_ISM:inst\|data_oe\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bus_ISM:inst\|state~14 1 REG LC9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns bus_ISM:inst\|data_oe 2 REG LC16 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 8; REG Node = 'bus_ISM:inst\|data_oe'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "8.000 ns" { bus_ISM:inst|state~14 bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "8.000 ns" { bus_ISM:inst|state~14 bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { bus_ISM:inst|state~14 bus_ISM:inst|data_oe } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { clk } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 360 -48 120 376 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns bus_ISM:inst\|data_oe 2 REG LC16 8 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC16; Fanout = 8; REG Node = 'bus_ISM:inst\|data_oe'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "0.000 ns" { clk bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|data_oe } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { clk } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 360 -48 120 376 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns bus_ISM:inst\|state~14 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "0.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|data_oe } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 12 -1 0 } }  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "8.000 ns" { bus_ISM:inst|state~14 bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { bus_ISM:inst|state~14 bus_ISM:inst|data_oe } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|data_oe } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|data_oe } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "bus_ISM:inst\|state~14 ALE_E clk 11.000 ns register " "Info: tsu for register \"bus_ISM:inst\|state~14\" (data pin = \"ALE_E\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns ALE_E 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { ALE_E } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 328 -48 120 344 "ALE_E" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns bus_ISM:inst\|state~14 2 REG LC9 9 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "7.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "10.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { ALE_E ALE_E~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { clk } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 360 -48 120 376 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns bus_ISM:inst\|state~14 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst\|state~14'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "0.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "10.000 ns" { ALE_E bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { ALE_E ALE_E~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { clk bus_ISM:inst|state~14 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out bus_ISM:inst|state~14 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ALE_E data_out10 decode:inst5\|reg_en\[0\] 24.000 ns register " "Info: tco from clock \"ALE_E\" to destination pin \"data_out10\" through register \"decode:inst5\|reg_en\[0\]\" is 24.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE_E source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"ALE_E\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns ALE_E 1 CLK PIN_83 7 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { ALE_E } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 328 -48 120 344 "ALE_E" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns decode:inst5\|reg_en\[0\] 2 REG LC26 129 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC26; Fanout = 129; REG Node = 'decode:inst5\|reg_en\[0\]'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "0.000 ns" { ALE_E decode:inst5|reg_en[0] } "NODE_NAME" } "" } } { "decode.v" "" { Text "E:/project/cpld_bus/decode.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { ALE_E decode:inst5|reg_en[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { ALE_E ALE_E~out decode:inst5|reg_en[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "decode.v" "" { Text "E:/project/cpld_bus/decode.v" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.000 ns + Longest register pin " "Info: + Longest register to pin delay is 20.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decode:inst5\|reg_en\[0\] 1 REG LC26 129 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 129; REG Node = 'decode:inst5\|reg_en\[0\]'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "" { decode:inst5|reg_en[0] } "NODE_NAME" } "" } } { "decode.v" "" { Text "E:/project/cpld_bus/decode.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns Output_reg:inst6\|always0~35 2 COMB LC8 8 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC8; Fanout = 8; COMB Node = 'Output_reg:inst6\|always0~35'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "9.000 ns" { decode:inst5|reg_en[0] Output_reg:inst6|always0~35 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(9.000 ns) 20.000 ns data_out10 3 PIN PIN_51 0 " "Info: 3: + IC(2.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'data_out10'" {  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "11.000 ns" { Output_reg:inst6|always0~35 data_out10 } "NODE_NAME" } "" } } { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 248 688 864 264 "data_out1\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 80.00 % " "Info: Total cell delay = 16.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 20.00 % " "Info: Total interconnect delay = 4.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "20.000 ns" { decode:inst5|reg_en[0] Output_reg:inst6|always0~35 data_out10 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "20.000 ns" { decode:inst5|reg_en[0] Output_reg:inst6|always0~35 data_out10 } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 9.000ns } } }  } 0}  } { { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "3.000 ns" { ALE_E decode:inst5|reg_en[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { ALE_E ALE_E~out decode:inst5|reg_en[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" "" { Report "E:/project/cpld_bus/db/cpld_bus_cmp.qrpt" Compiler "cpld_bus" "UNKNOWN" "V1" "E:/project/cpld_bus/db/cpld_bus.quartus_db" { Floorplan "E:/project/cpld_bus/" "" "20.000 ns" { decode:inst5|reg_en[0] Output_reg:inst6|always0~35 data_out10 } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "20.000 ns" { decode:inst5|reg_en[0] Output_reg:inst6|always0~35 data_out10 } { 0.000ns 2.000ns 2.000ns } { 0.000ns 7.000ns 9.000ns } } }  } 0}