cpld_bus.hier_info

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

|cpld_bus
addr_data[0] <= inst9[0]
addr_data[0] <= Output_reg:inst6.addr_data[0]
addr_data[0] <= bus_ISM:inst.addr_data[0]
addr_data[0] <= decode:inst5.addr_data[0]
addr_data[0] <= Output_reg:inst7.addr_data[0]
addr_data[0] <= Output_reg:inst4.addr_data[0]
addr_data[0] <= Output_reg:inst8.addr_data[0]
addr_data[1] <= inst9[1]
addr_data[1] <= Output_reg:inst6.addr_data[1]
addr_data[1] <= bus_ISM:inst.addr_data[1]
addr_data[1] <= decode:inst5.addr_data[1]
addr_data[1] <= Output_reg:inst7.addr_data[1]
addr_data[1] <= Output_reg:inst4.addr_data[1]
addr_data[1] <= Output_reg:inst8.addr_data[1]
addr_data[2] <= inst9[2]
addr_data[2] <= Output_reg:inst6.addr_data[2]
addr_data[2] <= bus_ISM:inst.addr_data[2]
addr_data[2] <= decode:inst5.addr_data[2]
addr_data[2] <= Output_reg:inst7.addr_data[2]
addr_data[2] <= Output_reg:inst4.addr_data[2]
addr_data[2] <= Output_reg:inst8.addr_data[2]
addr_data[3] <= inst9[3]
addr_data[3] <= Output_reg:inst6.addr_data[3]
addr_data[3] <= bus_ISM:inst.addr_data[3]
addr_data[3] <= decode:inst5.addr_data[3]
addr_data[3] <= Output_reg:inst7.addr_data[3]
addr_data[3] <= Output_reg:inst4.addr_data[3]
addr_data[3] <= Output_reg:inst8.addr_data[3]
addr_data[4] <= inst9[4]
addr_data[4] <= Output_reg:inst6.addr_data[4]
addr_data[4] <= bus_ISM:inst.addr_data[4]
addr_data[4] <= decode:inst5.addr_data[4]
addr_data[4] <= Output_reg:inst7.addr_data[4]
addr_data[4] <= Output_reg:inst4.addr_data[4]
addr_data[4] <= Output_reg:inst8.addr_data[4]
addr_data[5] <= inst9[5]
addr_data[5] <= Output_reg:inst6.addr_data[5]
addr_data[5] <= bus_ISM:inst.addr_data[5]
addr_data[5] <= decode:inst5.addr_data[5]
addr_data[5] <= Output_reg:inst7.addr_data[5]
addr_data[5] <= Output_reg:inst4.addr_data[5]
addr_data[5] <= Output_reg:inst8.addr_data[5]
addr_data[6] <= inst9[6]
addr_data[6] <= Output_reg:inst6.addr_data[6]
addr_data[6] <= bus_ISM:inst.addr_data[6]
addr_data[6] <= decode:inst5.addr_data[6]
addr_data[6] <= Output_reg:inst7.addr_data[6]
addr_data[6] <= Output_reg:inst4.addr_data[6]
addr_data[6] <= Output_reg:inst8.addr_data[6]
addr_data[7] <= inst9[7]
addr_data[7] <= Output_reg:inst6.addr_data[7]
addr_data[7] <= bus_ISM:inst.addr_data[7]
addr_data[7] <= decode:inst5.addr_data[7]
addr_data[7] <= Output_reg:inst7.addr_data[7]
addr_data[7] <= Output_reg:inst4.addr_data[7]
addr_data[7] <= Output_reg:inst8.addr_data[7]
PSEN_N => bus_ISM:inst.PSEN_N
PSEN_N => decode:inst5.PSEN_N
ALE_E => bus_ISM:inst.ALE_E
ALE_E => decode:inst5.ALE_E
reset => bus_ISM:inst.reset
clk => bus_ISM:inst.clk
WR_N => bus_ISM:inst.WR_N
WR_N => Output_reg:inst6.WR_N
WR_N => Output_reg:inst7.WR_N
WR_N => Output_reg:inst4.WR_N
WR_N => Output_reg:inst8.WR_N
RD_N => bus_ISM:inst.RD_N
RD_N => Data_Out_Mux:inst1.RD_N
addr[8] => decode:inst5.addr[8]
addr[9] => decode:inst5.addr[9]
addr[10] => decode:inst5.addr[10]
addr[11] => decode:inst5.addr[11]
addr[12] => decode:inst5.addr[12]
addr[13] => decode:inst5.addr[13]
addr[14] => decode:inst5.addr[14]
addr[15] => decode:inst5.addr[15]
data_out7 <= Data_Out_Mux:inst1.data_out[7]
data_out6 <= Data_Out_Mux:inst1.data_out[6]
data_out5 <= Data_Out_Mux:inst1.data_out[5]
data_out4 <= Data_Out_Mux:inst1.data_out[4]
data_out3 <= Data_Out_Mux:inst1.data_out[3]
data_out2 <= Data_Out_Mux:inst1.data_out[2]
data_out1 <= Data_Out_Mux:inst1.data_out[1]
data_out0 <= Data_Out_Mux:inst1.data_out[0]
data_out17 <= Output_reg:inst6.data_out[7]
data_out16 <= Output_reg:inst6.data_out[6]
data_out15 <= Output_reg:inst6.data_out[5]
data_out14 <= Output_reg:inst6.data_out[4]
data_out13 <= Output_reg:inst6.data_out[3]
data_out12 <= Output_reg:inst6.data_out[2]
data_out11 <= Output_reg:inst6.data_out[1]
data_out10 <= Output_reg:inst6.data_out[0]
data_out27 <= Output_reg:inst7.data_out[7]
data_out26 <= Output_reg:inst7.data_out[6]
data_out25 <= Output_reg:inst7.data_out[5]
data_out24 <= Output_reg:inst7.data_out[4]
data_out23 <= Output_reg:inst7.data_out[3]
data_out22 <= Output_reg:inst7.data_out[2]
data_out21 <= Output_reg:inst7.data_out[1]
data_out20 <= Output_reg:inst7.data_out[0]
data_out37 <= Output_reg:inst4.data_out[7]
data_out36 <= Output_reg:inst4.data_out[6]
data_out35 <= Output_reg:inst4.data_out[5]
data_out34 <= Output_reg:inst4.data_out[4]
data_out33 <= Output_reg:inst4.data_out[3]
data_out32 <= Output_reg:inst4.data_out[2]
data_out31 <= Output_reg:inst4.data_out[1]
data_out30 <= Output_reg:inst4.data_out[0]
data_out47 <= Output_reg:inst8.data_out[7]
data_out46 <= Output_reg:inst8.data_out[6]
data_out45 <= Output_reg:inst8.data_out[5]
data_out44 <= Output_reg:inst8.data_out[4]
data_out43 <= Output_reg:inst8.data_out[3]
data_out42 <= Output_reg:inst8.data_out[2]
data_out41 <= Output_reg:inst8.data_out[1]
data_out40 <= Output_reg:inst8.data_out[0]


|cpld_bus|Data_Out_Mux:inst1
Data_inA[0] => Select~7.IN1
Data_inA[1] => Select~6.IN1
Data_inA[2] => Select~5.IN1
Data_inA[3] => Select~4.IN1
Data_inA[4] => Select~3.IN1
Data_inA[5] => Select~2.IN1
Data_inA[6] => Select~1.IN1
Data_inA[7] => Select~0.IN1
Data_inB[0] => Select~7.IN2
Data_inB[1] => Select~6.IN2
Data_inB[2] => Select~5.IN2
Data_inB[3] => Select~4.IN2
Data_inB[4] => Select~3.IN2
Data_inB[5] => Select~2.IN2
Data_inB[6] => Select~1.IN2
Data_inB[7] => Select~0.IN2
Data_inC[0] => Select~7.IN3
Data_inC[1] => Select~6.IN3
Data_inC[2] => Select~5.IN3
Data_inC[3] => Select~4.IN3
Data_inC[4] => Select~3.IN3
Data_inC[5] => Select~2.IN3
Data_inC[6] => Select~1.IN3
Data_inC[7] => Select~0.IN3
Data_inD[0] => Select~7.IN4
Data_inD[1] => Select~6.IN4
Data_inD[2] => Select~5.IN4
Data_inD[3] => Select~4.IN4
Data_inD[4] => Select~3.IN4
Data_inD[5] => Select~2.IN4
Data_inD[6] => Select~1.IN4
Data_inD[7] => Select~0.IN4
data_trs => always0~1.IN0
RD_N => always0~0.IN0
reg_en[0] => Decoder~0.IN3
reg_en[1] => Decoder~0.IN2
reg_en[2] => Decoder~0.IN1
reg_en[3] => Decoder~0.IN0
data_out[0] <= data_out~7.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out~3.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out~2.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out~1.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out~0.DB_MAX_OUTPUT_PORT_TYPE


|cpld_bus|bus_ISM:inst
PSEN_N => always1~1.IN0
ALE_E => always1~0.IN0
ALE_E => next_state~20.OUTPUTSELECT
ALE_E => next_state~21.OUTPUTSELECT
ALE_E => next_state~22.OUTPUTSELECT
ALE_E => next_state~23.OUTPUTSELECT
addr_data[0] <= <UNC>
addr_data[1] <= <UNC>
addr_data[2] <= <UNC>
addr_data[3] <= <UNC>
addr_data[4] <= <UNC>
addr_data[5] <= <UNC>
addr_data[6] <= <UNC>
addr_data[7] <= <UNC>
WR_N => always1~6.IN0
WR_N => always1~7.IN0
RD_N => always1~5.IN0
RD_N => always1~7.IN1
addr_match => always1~2.IN0
addr_match => always1~4.IN0
data_trs <= data_trs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_oe <= data_oe~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => data_oe~reg0.CLK
clk => data_trs~reg0.CLK
clk => state~0.IN1
reset => always0~0.IN0


|cpld_bus|decode:inst5
addr[8] => reduce_nor~0.IN7
addr[9] => reduce_nor~0.IN6
addr[10] => reduce_nor~0.IN5
addr[11] => reduce_nor~0.IN4
addr[12] => reduce_nor~0.IN3
addr[13] => reduce_nor~0.IN2
addr[14] => reduce_nor~0.IN1
addr[15] => reduce_nor~0.IN0
ALE_E => always0~0.IN0
PSEN_N => ~NO_FANOUT~
reg_en[0] <= reg_en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_en[1] <= reg_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_en[2] <= reg_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reg_en[3] <= reg_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr_match <= addr_match~0.DB_MAX_OUTPUT_PORT_TYPE


|cpld_bus|Output_reg:inst6
reg_en => always0~0.IN0
data_trs => always0~0.IN1
WR_N => always0~1.IN0
data_out[0] <= always0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= always0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= always0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= always0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= always0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= always0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= always0~3.DB_MAX_OUTPUT_PORT_TYPE


|cpld_bus|Output_reg:inst7
reg_en => always0~0.IN0
data_trs => always0~0.IN1
WR_N => always0~1.IN0
data_out[0] <= always0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= always0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= always0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= always0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= always0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= always0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= always0~3.DB_MAX_OUTPUT_PORT_TYPE


|cpld_bus|Output_reg:inst4
reg_en => always0~0.IN0
data_trs => always0~0.IN1
WR_N => always0~1.IN0
data_out[0] <= always0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= always0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= always0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= always0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= always0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= always0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= always0~3.DB_MAX_OUTPUT_PORT_TYPE


|cpld_bus|Output_reg:inst8
reg_en => always0~0.IN0
data_trs => always0~0.IN1
WR_N => always0~1.IN0
data_out[0] <= always0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= always0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= always0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= always0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= always0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= always0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= always0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= always0~3.DB_MAX_OUTPUT_PORT_TYPE