cpld_bus.hif

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

Version 4.2 Build 156 11/29/2004 SJ Web Edition
29
1485
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Off
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Off
STATE_MACHINE_PROCESSING
Auto
STRATIXII_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONE_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONEII_OPTIMIZATION_TECHNIQUE
Balanced
STRATIX_OPTIMIZATION_TECHNIQUE
Balanced
MAXII_OPTIMIZATION_TECHNIQUE
Balanced
----
-- End Partition --
# entity
Data_Out_Mux
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
data_out_mux.v
1123071658
7
# storage
db|cpld_bus.(1).cnf
db|cpld_bus.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
bus_ISM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
bus_ISM.v
1123069584
7
# storage
db|cpld_bus.(2).cnf
db|cpld_bus.(2).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
idle
0
PARAMETER_UNKNOWN
USR
ADDR_decode
1
PARAMETER_UNKNOWN
USR
data_trs_state
2
PARAMETER_UNKNOWN
USR
end_cycle
3
PARAMETER_UNKNOWN
USR
}
# end
# entity
Output_reg
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Output_reg.v
1123069246
7
# storage
db|cpld_bus.(4).cnf
db|cpld_bus.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# end
# entity
cpld_bus
# case_insensitive
# source_file
cpld_bus.bdf
1123157066
23
# storage
db|cpld_bus.(0).cnf
db|cpld_bus.(0).cnf
# end
# entity
decode
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
decode.v
1123157046
7
# storage
db|cpld_bus.(3).cnf
db|cpld_bus.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
BASE_ADDR
0
PARAMETER_UNKNOWN
USR
STATUS_REG
BASE_ADDR+8'b10000000
PARAMETER_UNKNOWN
USR
CONTROL_REG
BASE_ADDR+8'b10000010
PARAMETER_UNKNOWN
USR
DATAIN_REG
BASE_ADDR+8'b10000100
PARAMETER_UNKNOWN
USR
DATAOUT_REG
BASE_ADDR+8'b10000110
PARAMETER_UNKNOWN
USR
}
# end
# complete