cpld_bus.fit.qmsg

来自「CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Qua」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 156 11/29/2004 SJ Web Edition " "Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 04 20:04:32 2005 " "Info: Processing started: Thu Aug 04 20:04:32 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off cpld_bus -c cpld_bus " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off cpld_bus -c cpld_bus" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "cpld_bus EPM7128SLC84-15 " "Info: Selected device EPM7128SLC84-15 for design \"cpld_bus\"" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 20:04:34 2005 " "Info: Processing ended: Thu Aug 04 20:04:34 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}