📄 cpld_bus.map.qmsg
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{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" { } { { "cpld_bus.bdf" "" { Schematic "E:/project/cpld_bus/cpld_bus.bdf" { { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } { 616 712 888 632 "data_out4\[7..0\]" "" } } } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data_inA data_out_mux.v(19) " "Warning: Verilog HDL Always Construct warning at data_out_mux.v(19): variable \"Data_inA\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "data_out_mux.v" "" { Text "E:/project/cpld_bus/data_out_mux.v" 19 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data_inB data_out_mux.v(20) " "Warning: Verilog HDL Always Construct warning at data_out_mux.v(20): variable \"Data_inB\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "data_out_mux.v" "" { Text "E:/project/cpld_bus/data_out_mux.v" 20 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data_inC data_out_mux.v(21) " "Warning: Verilog HDL Always Construct warning at data_out_mux.v(21): variable \"Data_inC\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "data_out_mux.v" "" { Text "E:/project/cpld_bus/data_out_mux.v" 21 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Data_inD data_out_mux.v(22) " "Warning: Verilog HDL Always Construct warning at data_out_mux.v(22): variable \"Data_inD\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "data_out_mux.v" "" { Text "E:/project/cpld_bus/data_out_mux.v" 22 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 decode.v(17) " "Warning: Verilog HDL assignment warning at decode.v(17): truncated value with size 2 to match size of target (1)" { } { { "decode.v" "" { Text "E:/project/cpld_bus/decode.v" 17 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "addr_data Output_reg.v(17) " "Warning: Verilog HDL Always Construct warning at Output_reg.v(17): variable \"addr_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 17 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "data Output_reg.v(12) " "Warning: Verilog HDL Always Construct warning at Output_reg.v(12): variable data may not be assigned a new value in every possible path through the Always Construct. Variable data holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 12 0 0 } } } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|cpld_bus\|bus_ISM:inst\|state 4 0 " "Info: State machine \"\|cpld_bus\|bus_ISM:inst\|state\" contains 4 states and 0 state bits" { } { } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|cpld_bus\|bus_ISM:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|cpld_bus\|bus_ISM:inst\|state\"" { } { } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|cpld_bus\|bus_ISM:inst\|state " "Info: Encoding result for state machine \"\|cpld_bus\|bus_ISM:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "2 " "Info: Completed encoding using 2 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "bus_ISM:inst\|state~15 " "Info: Encoded state bit \"bus_ISM:inst\|state~15\"" { } { } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "bus_ISM:inst\|state~14 " "Info: Encoded state bit \"bus_ISM:inst\|state~14\"" { } { } 0} } { } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpld_bus\|bus_ISM:inst\|state.idle 00 " "Info: State \"\|cpld_bus\|bus_ISM:inst\|state.idle\" uses code string \"00\"" { } { { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 18 -1 0 } } } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpld_bus\|bus_ISM:inst\|state.data_trs_state 10 " "Info: State \"\|cpld_bus\|bus_ISM:inst\|state.data_trs_state\" uses code string \"10\"" { } { { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 18 -1 0 } } } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpld_bus\|bus_ISM:inst\|state.ADDR_decode 01 " "Info: State \"\|cpld_bus\|bus_ISM:inst\|state.ADDR_decode\" uses code string \"01\"" { } { { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 18 -1 0 } } } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|cpld_bus\|bus_ISM:inst\|state.end_cycle 11 " "Info: State \"\|cpld_bus\|bus_ISM:inst\|state.end_cycle\" uses code string \"11\"" { } { { "bus_ISM.v" "" { Text "E:/project/cpld_bus/bus_ISM.v" 18 -1 0 } } } 0} } { } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[7\]~0 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[7\]~0\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[7\]~0 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[7\]~0\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[7\]~0 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[7\]~0\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[7\]~0 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[7\]~0\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[6\]~1 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[6\]~1\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[6\]~1 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[6\]~1\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[6\]~1 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[6\]~1\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[6\]~1 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[6\]~1\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[5\]~2 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[5\]~2\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[5\]~2 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[5\]~2\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[5\]~2 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[5\]~2\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[5\]~2 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[5\]~2\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[4\]~3 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[4\]~3\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[4\]~3 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[4\]~3\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[4\]~3 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[4\]~3\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[4\]~3 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[4\]~3\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[3\]~4 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[3\]~4\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[3\]~4 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[3\]~4\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[3\]~4 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[3\]~4\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[3\]~4 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[3\]~4\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[2\]~5 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[2\]~5\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[2\]~5 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[2\]~5\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[2\]~5 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[2\]~5\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[2\]~5 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[2\]~5\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[1\]~6 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[1\]~6\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[1\]~6 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[1\]~6\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[1\]~6 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[1\]~6\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[1\]~6 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[1\]~6\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst6\|data_out\[0\]~7 " "Warning: Converting TRI node \"Output_reg:inst6\|data_out\[0\]~7\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst7\|data_out\[0\]~7 " "Warning: Converting TRI node \"Output_reg:inst7\|data_out\[0\]~7\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst4\|data_out\[0\]~7 " "Warning: Converting TRI node \"Output_reg:inst4\|data_out\[0\]~7\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "Output_reg:inst8\|data_out\[0\]~7 " "Warning: Converting TRI node \"Output_reg:inst8\|data_out\[0\]~7\" that feeds logic to an OR gate" { } { { "Output_reg.v" "" { Text "E:/project/cpld_bus/Output_reg.v" 4 -1 0 } } } 0} } { } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" { } { } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "ALE_E " "Info: Promoted clock signal driven by pin \"ALE_E\" to global clock signal" { } { } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" { } { } 0} } { } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "138 " "Info: Implemented 138 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "40 " "Info: Implemented 40 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" { } { } 0} { "Info" "ISCL_SCL_TM_MCELLS" "76 " "Info: Implemented 76 macrocells" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 49 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 20:04:30 2005 " "Info: Processing ended: Thu Aug 04 20:04:30 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0} } { } 0}
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