cpld_bus.sim.qmsg

来自「CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Qua」· QMSG 代码 · 共 8 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 156 11/29/2004 SJ Web Edition " "Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 04 20:09:06 2005 " "Info: Processing started: Thu Aug 04 20:09:06 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off cpld_bus -c cpld_bus " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off cpld_bus -c cpld_bus" {  } {  } 0}
{ "Info" "ISIM_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      9.63 % " "Info: Simulation coverage is       9.63 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "265 " "Info: Number of transitions in simulation is 265" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 04 20:09:07 2005 " "Info: Processing ended: Thu Aug 04 20:09:07 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}