cpld_bus.map.summary

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

Flow Status : Successful - Thu Aug 04 20:04:30 2005
Quartus II Version : 4.2 Build 156 11/29/2004 SJ Web Edition
Revision Name : cpld_bus
Top-level Entity Name : cpld_bus
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 76
Total pins : 62