output_reg.v

来自「CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Qua」· Verilog 代码 · 共 21 行

module Output_reg(reg_en,addr_data,data_trs,WR_N,data_out);
	input                reg_en;
	inout [7:0]          addr_data;
	output[7:0]          data_out;
	input                data_trs;
	input                WR_N;

	reg [7:0]            data;    
	reg [7:0]            addr_data;
	reg [7:0]            data_out;

	always @(reg_en or data_trs or WR_N)

		
		if((reg_en==1) && (data_trs==1)&&(WR_N==0))
		begin
			data = addr_data;
			data_out = data;
		end
		else data_out = 8'bzzzzzzzz;
endmodule