cpld_bus.map.eqn

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

--C1L92 is Data_Out_Mux:inst1|data_out[7]~4307
C1L92_p0_out = WR_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & B1_data_trs & !RD_N;
C1L92_p1_out = WR_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L92_p2_out = !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N & A1L91;
C1L92_p3_out = !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & B1_data_trs & !RD_N & A1L91;
C1L92_p4_out = WR_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L92_or_out = C1L13 # C1L92_p0_out # C1L92_p1_out # C1L92_p2_out # C1L92_p3_out # C1L92_p4_out;
C1L92 = C1L92_or_out;


--C1L52 is Data_Out_Mux:inst1|data_out[6]~4313
C1L52_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L02;
C1L52_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L52_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L52_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L52_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L52_or_out = C1L72 # C1L52_p0_out # C1L52_p1_out # C1L52_p2_out # C1L52_p3_out # C1L52_p4_out;
C1L52 = C1L52_or_out;


--C1L12 is Data_Out_Mux:inst1|data_out[5]~4319
C1L12_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L12;
C1L12_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L12_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L12_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L12_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L12_or_out = C1L32 # C1L12_p0_out # C1L12_p1_out # C1L12_p2_out # C1L12_p3_out # C1L12_p4_out;
C1L12 = C1L12_or_out;


--C1L71 is Data_Out_Mux:inst1|data_out[4]~4325
C1L71_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L22;
C1L71_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L71_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L71_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L71_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L71_or_out = C1L91 # C1L71_p0_out # C1L71_p1_out # C1L71_p2_out # C1L71_p3_out # C1L71_p4_out;
C1L71 = C1L71_or_out;


--C1L31 is Data_Out_Mux:inst1|data_out[3]~4331
C1L31_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L32;
C1L31_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L31_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L31_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L31_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L31_or_out = C1L51 # C1L31_p0_out # C1L31_p1_out # C1L31_p2_out # C1L31_p3_out # C1L31_p4_out;
C1L31 = C1L31_or_out;


--C1L9 is Data_Out_Mux:inst1|data_out[2]~4337
C1L9_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L42;
C1L9_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L9_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L9_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L9_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L9_or_out = C1L11 # C1L9_p0_out # C1L9_p1_out # C1L9_p2_out # C1L9_p3_out # C1L9_p4_out;
C1L9 = C1L9_or_out;


--C1L5 is Data_Out_Mux:inst1|data_out[1]~4343
C1L5_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L52;
C1L5_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L5_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L5_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L5_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L5_or_out = C1L7 # C1L5_p0_out # C1L5_p1_out # C1L5_p2_out # C1L5_p3_out # C1L5_p4_out;
C1L5 = C1L5_or_out;


--C1L1 is Data_Out_Mux:inst1|data_out[0]~4349
C1L1_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L62;
C1L1_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L1_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L1_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L1_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L1_or_out = C1L3 # C1L1_p0_out # C1L1_p1_out # C1L1_p2_out # C1L1_p3_out # C1L1_p4_out;
C1L1 = C1L1_or_out;


--E1_reg_en[3] is decode:inst5|reg_en[3]
E1_reg_en[3]_p1_out = A1L52 & A1L42 & A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L62;
E1_reg_en[3]_or_out = E1_reg_en[3]_p1_out;
E1_reg_en[3]_reg_input = E1_reg_en[3]_or_out;
E1_reg_en[3] = DFFE(E1_reg_en[3]_reg_input, !GLOBAL(ALE_E), , , );


--B1L4Q is bus_ISM:inst|state~15
B1L4Q_p1_out = WR_N & RD_N & !B1L3Q & B1L4Q;
B1L4Q_p2_out = !WR_N & B1L3Q & !B1L4Q & !addr[15] & !addr[14] & !addr[13] & !addr[12] & !addr[11] & !addr[10] & !addr[9] & !addr[8];
B1L4Q_p3_out = !RD_N & B1L3Q & !B1L4Q & !addr[15] & !addr[14] & !addr[13] & !addr[12] & !addr[11] & !addr[10] & !addr[9] & !addr[8];
B1L4Q_p4_out = B1L3Q & B1L4Q & !GLOBAL(ALE_E);
B1L4Q_or_out = B1L4Q_p1_out # B1L4Q_p2_out # B1L4Q_p3_out # B1L4Q_p4_out;
B1L4Q_reg_input = B1L4Q_or_out;
B1L4Q = DFFE(B1L4Q_reg_input, GLOBAL(clk), GLOBAL(reset), , );


--B1L3Q is bus_ISM:inst|state~14
B1L3Q_p1_out = B1L4Q & !B1L3Q;
B1L3Q_p2_out = !B1L4Q & B1L3Q & WR_N & RD_N & !addr[15] & !addr[14] & !addr[13] & !addr[12] & !addr[11] & !addr[10] & !addr[9] & !addr[8];
B1L3Q_p3_out = B1L4Q & !GLOBAL(ALE_E);
B1L3Q_p4_out = !B1L3Q & !GLOBAL(ALE_E) & PSEN_N;
B1L3Q_or_out = B1L3Q_p1_out # B1L3Q_p2_out # B1L3Q_p3_out # B1L3Q_p4_out;
B1L3Q_reg_input = B1L3Q_or_out;
B1L3Q = DFFE(B1L3Q_reg_input, GLOBAL(clk), GLOBAL(reset), , );


--B1_data_oe is bus_ISM:inst|data_oe
B1_data_oe_p1_out = !RD_N & B1L3Q & !B1L4Q & !addr[15] & !addr[14] & !addr[13] & !addr[12] & !addr[11] & !addr[10] & !addr[9] & !addr[8];
B1_data_oe_or_out = B1_data_oe_p1_out;
B1_data_oe_reg_input = B1_data_oe_or_out;
B1_data_oe = DFFE(B1_data_oe_reg_input, GLOBAL(clk), , , GLOBAL(reset));


--B1_data_trs is bus_ISM:inst|data_trs
B1_data_trs_p1_out = RD_N & !WR_N & B1L3Q & !B1L4Q & !addr[15] & !addr[14] & !addr[13] & !addr[12] & !addr[11] & !addr[10] & !addr[9] & !addr[8];
B1_data_trs_or_out = B1_data_trs_p1_out;
B1_data_trs_reg_input = B1_data_trs_or_out;
B1_data_trs = DFFE(B1_data_trs_reg_input, GLOBAL(clk), , , GLOBAL(reset));


--D4L1 is Output_reg:inst8|always0~45
D4L1_p1_out = B1_data_trs & !WR_N & E1_reg_en[3];
D4L1_or_out = D4L1_p1_out;
D4L1 = D4L1_or_out;


--A1L72 is addr_data~424
A1L72_or_out = A1L91;
A1L72 = A1L72_or_out;


--A1L82 is addr_data~426
A1L82_or_out = A1L91;
A1L82 = A1L82_or_out;


--A1L92 is addr_data~428
A1L92_or_out = A1L91;
A1L92 = A1L92_or_out;


--A1L03 is addr_data~430
A1L03_or_out = A1L91;
A1L03 = A1L03_or_out;


--C1L62 is Data_Out_Mux:inst1|data_out[6]~4355
C1L62_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L02;
C1L62_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L62_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L62_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L62_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L62_or_out = C1L82 # C1L62_p0_out # C1L62_p1_out # C1L62_p2_out # C1L62_p3_out # C1L62_p4_out;
C1L62 = C1L62_or_out;


--C1L22 is Data_Out_Mux:inst1|data_out[5]~4361
C1L22_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L12;
C1L22_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L22_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L22_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L22_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L22_or_out = C1L42 # C1L22_p0_out # C1L22_p1_out # C1L22_p2_out # C1L22_p3_out # C1L22_p4_out;
C1L22 = C1L22_or_out;


--C1L81 is Data_Out_Mux:inst1|data_out[4]~4367
C1L81_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L22;
C1L81_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L81_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L81_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L81_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L81_or_out = C1L02 # C1L81_p0_out # C1L81_p1_out # C1L81_p2_out # C1L81_p3_out # C1L81_p4_out;
C1L81 = C1L81_or_out;


--C1L41 is Data_Out_Mux:inst1|data_out[3]~4373
C1L41_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L32;
C1L41_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L41_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L41_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L41_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L41_or_out = C1L61 # C1L41_p0_out # C1L41_p1_out # C1L41_p2_out # C1L41_p3_out # C1L41_p4_out;
C1L41 = C1L41_or_out;


--C1L01 is Data_Out_Mux:inst1|data_out[2]~4379
C1L01_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L42;
C1L01_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L01_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L01_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L01_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L01_or_out = C1L21 # C1L01_p0_out # C1L01_p1_out # C1L01_p2_out # C1L01_p3_out # C1L01_p4_out;
C1L01 = C1L01_or_out;


--C1L2 is Data_Out_Mux:inst1|data_out[0]~4385
C1L2_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L62;
C1L2_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L2_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L2_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L2_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L2_or_out = C1L4 # C1L2_p0_out # C1L2_p1_out # C1L2_p2_out # C1L2_p3_out # C1L2_p4_out;
C1L2 = C1L2_or_out;


--A1L13 is addr_data~432
A1L13_or_out = A1L02;
A1L13 = A1L13_or_out;


--A1L23 is addr_data~434
A1L23_or_out = A1L02;
A1L23 = A1L23_or_out;


--A1L33 is addr_data~436
A1L33_or_out = A1L02;
A1L33 = A1L33_or_out;


--A1L43 is addr_data~438
A1L43_or_out = A1L12;
A1L43 = A1L43_or_out;


--A1L53 is addr_data~440
A1L53_or_out = A1L12;
A1L53 = A1L53_or_out;


--A1L63 is addr_data~442
A1L63_or_out = A1L12;
A1L63 = A1L63_or_out;


--A1L73 is addr_data~444
A1L73_or_out = A1L22;
A1L73 = A1L73_or_out;


--A1L83 is addr_data~446
A1L83_or_out = A1L22;
A1L83 = A1L83_or_out;


--A1L93 is addr_data~448
A1L93_or_out = A1L22;
A1L93 = A1L93_or_out;


--A1L04 is addr_data~450
A1L04_or_out = A1L32;
A1L04 = A1L04_or_out;


--A1L14 is addr_data~452
A1L14_or_out = A1L32;
A1L14 = A1L14_or_out;


--A1L24 is addr_data~454
A1L24_or_out = A1L32;
A1L24 = A1L24_or_out;


--A1L34 is addr_data~456
A1L34_or_out = A1L42;
A1L34 = A1L34_or_out;


--A1L44 is addr_data~458
A1L44_or_out = A1L42;
A1L44 = A1L44_or_out;


--A1L54 is addr_data~460
A1L54_or_out = A1L42;
A1L54 = A1L54_or_out;


--A1L64 is addr_data~462
A1L64_or_out = A1L62;
A1L64 = A1L64_or_out;


--A1L74 is addr_data~464
A1L74_or_out = A1L62;
A1L74 = A1L74_or_out;


--A1L84 is addr_data~466
A1L84_or_out = A1L62;
A1L84 = A1L84_or_out;


--A1L94 is addr_data~468
A1L94_or_out = A1L02;
A1L94 = A1L94_or_out;


--A1L05 is addr_data~470
A1L05_or_out = A1L12;
A1L05 = A1L05_or_out;


--A1L15 is addr_data~472
A1L15_or_out = A1L22;
A1L15 = A1L15_or_out;


--A1L25 is addr_data~474
A1L25_or_out = A1L32;
A1L25 = A1L25_or_out;


--A1L35 is addr_data~476
A1L35_or_out = A1L42;
A1L35 = A1L35_or_out;


--A1L45 is addr_data~478
A1L45_or_out = A1L62;