cpld_bus.fit.rpt

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

; bus_ISM:inst|state~15               ; 4       ;
; PSEN_N                              ; 1       ;
; Data_Out_Mux:inst1|data_out[7]~4458 ; 1       ;
; Data_Out_Mux:inst1|data_out[1]~4454 ; 1       ;
; Data_Out_Mux:inst1|data_out[0]~4450 ; 1       ;
; Data_Out_Mux:inst1|data_out[2]~4446 ; 1       ;
; Data_Out_Mux:inst1|data_out[3]~4442 ; 1       ;
; Data_Out_Mux:inst1|data_out[4]~4438 ; 1       ;
; Data_Out_Mux:inst1|data_out[5]~4434 ; 1       ;
; Data_Out_Mux:inst1|data_out[6]~4430 ; 1       ;
; Data_Out_Mux:inst1|data_out[0]~4426 ; 1       ;
; Data_Out_Mux:inst1|data_out[1]~4422 ; 1       ;
; Data_Out_Mux:inst1|data_out[2]~4418 ; 1       ;
; Data_Out_Mux:inst1|data_out[3]~4414 ; 1       ;
; Data_Out_Mux:inst1|data_out[4]~4410 ; 1       ;
; Data_Out_Mux:inst1|data_out[5]~4406 ; 1       ;
; Data_Out_Mux:inst1|data_out[6]~4402 ; 1       ;
; Data_Out_Mux:inst1|data_out[7]~4398 ; 1       ;
; Data_Out_Mux:inst1|data_out[7]~4397 ; 1       ;
; addr_data~486                       ; 1       ;
; addr_data~484                       ; 1       ;
+-------------------------------------+---------+


+------------------------------------------------+
; Interconnect Usage Summary                     ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage             ;
+----------------------------+-------------------+
; Output enables             ; 5 / 6 ( 83 % )    ;
; PIA buffers                ; 57 / 288 ( 19 % ) ;
; PIAs                       ; 78 / 288 ( 27 % ) ;
+----------------------------+-------------------+


+----------------------------------------------------------------------------+
; LAB External Interconnect                                                  ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects  (Average = 9.75) ; Number of LABs  (Total = 8) ;
+----------------------------------------------+-----------------------------+
; 0 - 1                                        ; 0                           ;
; 2 - 3                                        ; 1                           ;
; 4 - 5                                        ; 1                           ;
; 6 - 7                                        ; 0                           ;
; 8 - 9                                        ; 4                           ;
; 10 - 11                                      ; 0                           ;
; 12 - 13                                      ; 0                           ;
; 14 - 15                                      ; 1                           ;
; 16 - 17                                      ; 0                           ;
; 18 - 19                                      ; 0                           ;
; 20 - 21                                      ; 0                           ;
; 22 - 23                                      ; 1                           ;
+----------------------------------------------+-----------------------------+


+----------------------------------------------------------------------+
; LAB Macrocells                                                       ;
+----------------------------------------+-----------------------------+
; Number of Macrocells  (Average = 9.50) ; Number of LABs  (Total = 8) ;
+----------------------------------------+-----------------------------+
; 0                                      ; 0                           ;
; 1                                      ; 0                           ;
; 2                                      ; 1                           ;
; 3                                      ; 0                           ;
; 4                                      ; 0                           ;
; 5                                      ; 0                           ;
; 6                                      ; 0                           ;
; 7                                      ; 1                           ;
; 8                                      ; 0                           ;
; 9                                      ; 1                           ;
; 10                                     ; 2                           ;
; 11                                     ; 1                           ;
; 12                                     ; 0                           ;
; 13                                     ; 1                           ;
; 14                                     ; 1                           ;
+----------------------------------------+-----------------------------+


+---------------------------------------------------------+
; Parallel Expander                                       ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0                        ; 0                            ;
; 1                        ; 16                           ;
+--------------------------+------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input                                                                                                                                                                                ; Output                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
;  A  ; LC10       ; addr_data[7], decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], bus_ISM:inst|data_trs, RD_N, WR_N                                      ; Data_Out_Mux:inst1|data_out[7]~4397                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
;  A  ; LC12       ; WR_N, bus_ISM:inst|data_trs, RD_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], addr_data[6]                                      ; Data_Out_Mux:inst1|data_out[6]~4355                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
;  A  ; LC4        ; WR_N, bus_ISM:inst|data_trs, RD_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], addr_data[6]                                      ; Data_Out_Mux:inst1|data_out[6]~4313                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
;  A  ; LC2        ; addr_data[7], decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], bus_ISM:inst|data_trs, RD_N, WR_N                                      ; Data_Out_Mux:inst1|data_out[7]~4307                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
;  A  ; LC11       ; Data_Out_Mux:inst1|data_out[7]~4458, WR_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], bus_ISM:inst|data_trs, RD_N, addr_data[7] ; data_out7                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
;  A  ; LC8        ; bus_ISM:inst|data_trs, WR_N, decode:inst5|reg_en[0]                                                                                                                                  ; data_out17, data_out16, data_out15, data_out14, data_out13, data_out12, data_out11, data_out10                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
;  A  ; LC13       ; Data_Out_Mux:inst1|data_out[6]~4430, bus_ISM:inst|data_trs, RD_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], addr_data[6], WR_N ; data_out6                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
;  A  ; LC6        ; addr_data[7]                                                                                                                                                                         ; data_out47                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
;  A  ; LC1        ; clk, RD_N, WR_N, bus_ISM:inst|state~14, bus_ISM:inst|state~15, addr[15], addr[14], addr[13], addr[12], addr[11], addr[10], addr[9], addr[8], reset                                   ; Data_Out_Mux:inst1|data_out[7]~4307, Data_Out_Mux:inst1|data_out[6]~4313, Data_Out_Mux:inst1|data_out[5]~4319, Data_Out_Mux:inst1|data_out[4]~4325, Data_Out_Mux:inst1|data_out[3]~4331, Data_Out_Mux:inst1|data_out[2]~4337, Data_Out_Mux:inst1|data_out[1]~4343, Data_Out_Mux:inst1|data_out[0]~4349, Output_reg:inst8|always0~45, Data_Out_Mux:inst1|data_out[6]~4355, Data_Out_Mux:inst1|data_out[5]~4361, Data_Out_Mux:inst1|data_out[4]~4367, Data_Out_Mux:inst1|data_out[3]~4373, Data_Out_Mux:inst1|data_out[2]~4379, Data_Out_Mux:inst1|data_out[0]~4385, Output_reg:inst7|always0~35, Output_reg:inst4|always0~43, Data_Out_Mux:inst1|data_out[1]~4391, Output_reg:inst6|always0~35, Data_Out_Mux:inst1|data_out[7]~4397, Data_Out_Mux:inst1|data_out[7]~4398, Data_Out_Mux:inst1|data_out[6]~4402, Data_Out_Mux:inst1|data_out[5]~4406, Data_Out_Mux:inst1|data_out[4]~4410, Data_Out_Mux:inst1|data_out[3]~4414, Data_Out_Mux:inst1|data_out[2]~4418, Data_Out_Mux:inst1|data_out[1]~4422, Data_Out_Mux:inst1|data_out[0]~4426, Data_Out_Mux:inst1|data_out[6]~4430, Data_Out_Mux:inst1|data_out[5]~4434, Data_Out_Mux:inst1|data_out[4]~4438, Data_Out_Mux:inst1|data_out[3]~4442, Data_Out_Mux:inst1|data_out[2]~4446, Data_Out_Mux:inst1|data_out[0]~4450, Data_Out_Mux:inst1|data_out[1]~4454, Data_Out_Mux:inst1|data_out[7]~4458 ;
;  A  ; LC16       ; clk, RD_N, bus_ISM:inst|state~14, bus_ISM:inst|state~15, addr[15], addr[14], addr[13], addr[12], addr[11], addr[10], addr[9], addr[8], reset                                         ; addr_data[7], addr_data[6], addr_data[5], addr_data[4], addr_data[3], addr_data[2], addr_data[1], addr_data[0]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
;  A  ; LC3        ; Data_Out_Mux:inst1|data_out[7]~4398, WR_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], bus_ISM:inst|data_trs, RD_N, addr_data[7] ; addr_data[7]                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
;  A  ; LC5        ; Data_Out_Mux:inst1|data_out[6]~4402, bus_ISM:inst|data_trs, RD_N, decode:inst5|reg_en[0], decode:inst5|reg_en[1], decode:inst5|reg_en[2], decode:inst5|reg_en[3], addr_data[6], WR_N ; addr_data[6]