data_out_mux.v

来自「CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Qua」· Verilog 代码 · 共 26 行

module Data_Out_Mux(Data_inA,Data_inB,Data_inC,Data_inD,data_trs,RD_N,reg_en,data_out);
input [7:0]    Data_inA;
input [7:0]    Data_inB;
input [7:0]    Data_inC;
input [7:0]    Data_inD;
input           data_trs;
input           RD_N;
input [3:0]   reg_en;
output[7:0]     data_out;

reg             data_trs;
reg             RD_N;
reg   [3:0]     reg_en;
reg   [7:0]     data_out;

always @(data_trs or RD_N or reg_en)
if(RD_N==0 & data_trs==1)
case (reg_en)
	1:             data_out = Data_inA;
	2:			   data_out = Data_inB;
	4:             data_out = Data_inC;
	8:             data_out = Data_inD;
	default:       data_out = 0;
endcase
else data_out = 0;
endmodule