bus_ism.v

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

 module bus_ISM(PSEN_N,ALE_E,addr_data,WR_N,
	RD_N,addr_match,data_trs,data_oe,clk,reset);

input PSEN_N,ALE_E;
input reset;
input clk;
inout [7:0]  addr_data;
input WR_N;
input RD_N;
input addr_match;
output data_trs;
output data_oe;
reg   data_trs;
reg   data_oe;
reg   data_trs_flag;
reg   data_oe_flag;

reg [1:0]   state,next_state;

parameter      idle = 0, ADDR_decode = 1, data_trs_state = 2, end_cycle = 3;

always @(posedge clk or negedge reset)
begin
/*reset*/
if(reset==0)
begin
	state<=idle;
		
end
else
begin
	state<=next_state;
	if(data_oe_flag==1)
		data_oe <=1;
	else data_oe<=0;
	if(data_trs_flag==1)
		data_trs<=1;
	else data_trs<=0;
end
end

/*状态转移*/	
always @(state or PSEN_N or ALE_E or WR_N or RD_N or addr_match)
begin
	next_state=state;
	data_oe_flag=0;
	data_trs_flag=0;
	case(state)
		idle:
		begin
		
			if((ALE_E==0)&&(PSEN_N==1))   
			begin
				next_state=ADDR_decode;
			end
		end
		ADDR_decode:
		begin
			if(addr_match==0)
			begin
				next_state=idle;
			end
			else if(((RD_N==0)||(WR_N==0))&&(addr_match==1))
			begin
				next_state=data_trs_state;
				if(RD_N==0)
					data_oe_flag=1;
				else if(WR_N==0)
					data_trs_flag=1;
				
			end
		end
		data_trs_state:
		begin
		if((RD_N==0)|(WR_N==0))
			begin	
				next_state=ADDR_decode;
			end
		else if((RD_N==1)|(WR_N==1))
			begin
				next_state = end_cycle;
				
			end
		end
		end_cycle:
		begin
	
		if(ALE_E==1)
			next_state=idle;
		end
		default:
			next_state=idle;
	endcase
end
endmodule