📄 cpld_bus.tan.rpt
字号:
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------------+------------------------+----------+
; N/A ; None ; -3.000 ns ; ALE_E ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; ALE_E ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr_data[0] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[0] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[0] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[0] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[3] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[3] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[3] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[3] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[4] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[4] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[4] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[4] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[5] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[5] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[5] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[5] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[6] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[6] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[6] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[6] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[7] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[7] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[7] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[7] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[2] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[2] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[2] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[2] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; PSEN_N ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; reset ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; reset ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[8] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[8] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[8] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[8] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[9] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[9] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[9] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[9] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[10] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[10] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[10] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[10] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[11] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[11] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[11] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[11] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[12] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[12] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[12] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[12] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[13] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[13] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[13] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[13] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[14] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[14] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[14] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[14] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr[15] ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; addr[15] ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; addr[15] ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; addr[15] ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; RD_N ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; RD_N ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; RD_N ; bus_ISM:inst|state~15 ; clk ;
; N/A ; None ; -3.000 ns ; RD_N ; bus_ISM:inst|data_oe ; clk ;
; N/A ; None ; -3.000 ns ; addr_data[1] ; decode:inst5|reg_en[0] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[1] ; decode:inst5|reg_en[1] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[1] ; decode:inst5|reg_en[2] ; ALE_E ;
; N/A ; None ; -3.000 ns ; addr_data[1] ; decode:inst5|reg_en[3] ; ALE_E ;
; N/A ; None ; -3.000 ns ; WR_N ; bus_ISM:inst|data_trs ; clk ;
; N/A ; None ; -3.000 ns ; WR_N ; bus_ISM:inst|state~14 ; clk ;
; N/A ; None ; -3.000 ns ; WR_N ; bus_ISM:inst|state~15 ; clk ;
+---------------+-------------+-----------+--------------+------------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition
Info: Processing started: Thu Aug 04 20:04:40 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cpld_bus -c cpld_bus
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "ALE_E" is an undefined clock
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "ALE_E"
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "bus_ISM:inst|state~14" and destination register "bus_ISM:inst|data_oe" (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 8; REG Node = 'bus_ISM:inst|data_oe'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC16; Fanout = 8; REG Node = 'bus_ISM:inst|data_oe'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock "clk" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "bus_ISM:inst|state~14" (data pin = "ALE_E", clock pin = "clk") is 11.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'
Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: Total cell delay = 9.000 ns ( 90.00 % )
Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "ALE_E" to destination pin "data_out10" through register "decode:inst5|reg_en[0]" is 24.000 ns
Info: + Longest clock path from clock "ALE_E" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC26; Fanout = 129; REG Node = 'decode:inst5|reg_en[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 20.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 129; REG Node = 'decode:inst5|reg_en[0]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC8; Fanout = 8; COMB Node = 'Output_reg:inst6|always0~35'
Info: 3: + IC(2.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'data_out10'
Info: Total cell delay = 16.000 ns ( 80.00 % )
Info: Total interconnect delay = 4.000 ns ( 20.00 % )
Info: Longest tpd from source pin "WR_N" to destination pin "data_out10" is 22.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 72; PIN Node = 'WR_N'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC8; Fanout = 8; COMB Node = 'Output_reg:inst6|always0~35'
Info: 3: + IC(2.000 ns) + CELL(9.000 ns) = 22.000 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'data_out10'
Info: Total cell delay = 18.000 ns ( 81.82 % )
Info: Total interconnect delay = 4.000 ns ( 18.18 % )
Info: th for register "bus_ISM:inst|state~14" (data pin = "ALE_E", clock pin = "clk") is -3.000 ns
Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 7; CLK Node = 'ALE_E'
Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC9; Fanout = 9; REG Node = 'bus_ISM:inst|state~14'
Info: Total cell delay = 9.000 ns ( 90.00 % )
Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Aug 04 20:04:40 2005
Info: Elapsed time: 00:00:01
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