cpld_bus.fit.eqn

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.

--E1_reg_en[2] is decode:inst5|reg_en[2] at LC22
E1_reg_en[2]_p1_out = !A1L52 & A1L42 & A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L62;
E1_reg_en[2]_or_out = E1_reg_en[2]_p1_out;
E1_reg_en[2]_reg_input = E1_reg_en[2]_or_out;
E1_reg_en[2] = DFFE(E1_reg_en[2]_reg_input, !GLOBAL(ALE_E), , , );


--E1_reg_en[1] is decode:inst5|reg_en[1] at LC23
E1_reg_en[1]_p1_out = A1L52 & !A1L42 & A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L62;
E1_reg_en[1]_or_out = E1_reg_en[1]_p1_out;
E1_reg_en[1]_reg_input = E1_reg_en[1]_or_out;
E1_reg_en[1] = DFFE(E1_reg_en[1]_reg_input, !GLOBAL(ALE_E), , , );


--D3L1 is Output_reg:inst7|always0~35 at LC117
D3L1_p1_out = B1_data_trs & !WR_N & E1_reg_en[1];
D3L1_or_out = D3L1_p1_out;
D3L1 = D3L1_or_out;


--D1L1 is Output_reg:inst4|always0~43 at LC115
D1L1_p1_out = B1_data_trs & !WR_N & E1_reg_en[2];
D1L1_or_out = D1L1_p1_out;
D1L1 = D1L1_or_out;


--C1L6 is Data_Out_Mux:inst1|data_out[1]~4391 at LC72
C1L6_p0_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & A1L52;
C1L6_p1_out = B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L6_p2_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & WR_N;
C1L6_p3_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L6_p4_out = B1_data_trs & !RD_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & WR_N;
C1L6_or_out = C1L8 # C1L6_p0_out # C1L6_p1_out # C1L6_p2_out # C1L6_p3_out # C1L6_p4_out;
C1L6 = C1L6_or_out;


--A1L55 is addr_data~480 at LC80
A1L55_or_out = A1L52;
A1L55 = A1L55_or_out;


--A1L65 is addr_data~482 at LC65
A1L65_or_out = A1L52;
A1L65 = A1L65_or_out;


--A1L75 is addr_data~484 at LC73
A1L75_or_out = A1L52;
A1L75 = A1L75_or_out;


--A1L85 is addr_data~486 at LC75
A1L85_or_out = A1L52;
A1L85 = A1L85_or_out;


--E1_reg_en[0] is decode:inst5|reg_en[0] at LC26
E1_reg_en[0]_p1_out = !A1L52 & !A1L42 & A1L91 & !A1L02 & !A1L12 & !A1L22 & !A1L32 & !A1L62;
E1_reg_en[0]_or_out = E1_reg_en[0]_p1_out;
E1_reg_en[0]_reg_input = E1_reg_en[0]_or_out;
E1_reg_en[0] = DFFE(E1_reg_en[0]_reg_input, !GLOBAL(ALE_E), , , );


--D2L1 is Output_reg:inst6|always0~35 at LC8
D2L1_p1_out = B1_data_trs & !WR_N & E1_reg_en[0];
D2L1_or_out = D2L1_p1_out;
D2L1 = D2L1_or_out;


--C1L03 is Data_Out_Mux:inst1|data_out[7]~4397 at LC11
C1L03_p0_out = WR_N & !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & B1_data_trs & !RD_N;
C1L03_p1_out = WR_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L03_p2_out = !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N & A1L91;
C1L03_p3_out = !E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & E1_reg_en[3] & B1_data_trs & !RD_N & A1L91;
C1L03_p4_out = WR_N & !E1_reg_en[0] & !E1_reg_en[1] & E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L03_or_out = C1L23 # C1L03_p0_out # C1L03_p1_out # C1L03_p2_out # C1L03_p3_out # C1L03_p4_out;
C1L03 = C1L03_or_out;


--C1L13 is Data_Out_Mux:inst1|data_out[7]~4398 at LC2
C1L13_p1_out = A1L91 & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L13_p2_out = A1L91 & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L13_p3_out = E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N & WR_N;
C1L13 = C1L13_p1_out # C1L13_p2_out # C1L13_p3_out;


--C1L72 is Data_Out_Mux:inst1|data_out[6]~4402 at LC4
C1L72_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L72_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L72_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L72 = C1L72_p1_out # C1L72_p2_out # C1L72_p3_out;


--C1L32 is Data_Out_Mux:inst1|data_out[5]~4406 at LC36
C1L32_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L32_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L32_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L32 = C1L32_p1_out # C1L32_p2_out # C1L32_p3_out;


--C1L91 is Data_Out_Mux:inst1|data_out[4]~4410 at LC82
C1L91_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L91_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L91_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L91 = C1L91_p1_out # C1L91_p2_out # C1L91_p3_out;


--C1L51 is Data_Out_Mux:inst1|data_out[3]~4414 at LC34
C1L51_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L51_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L51_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L51 = C1L51_p1_out # C1L51_p2_out # C1L51_p3_out;


--C1L11 is Data_Out_Mux:inst1|data_out[2]~4418 at LC50
C1L11_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L11_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L11_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L11 = C1L11_p1_out # C1L11_p2_out # C1L11_p3_out;


--C1L7 is Data_Out_Mux:inst1|data_out[1]~4422 at LC68
C1L7_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L7_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L7_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L7 = C1L7_p1_out # C1L7_p2_out # C1L7_p3_out;


--C1L3 is Data_Out_Mux:inst1|data_out[0]~4426 at LC66
C1L3_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L3_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L3_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L3 = C1L3_p1_out # C1L3_p2_out # C1L3_p3_out;


--C1L82 is Data_Out_Mux:inst1|data_out[6]~4430 at LC12
C1L82_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L82_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L02;
C1L82_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L82 = C1L82_p1_out # C1L82_p2_out # C1L82_p3_out;


--C1L42 is Data_Out_Mux:inst1|data_out[5]~4434 at LC18
C1L42_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L42_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L12;
C1L42_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L42 = C1L42_p1_out # C1L42_p2_out # C1L42_p3_out;


--C1L02 is Data_Out_Mux:inst1|data_out[4]~4438 at LC84
C1L02_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L02_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L22;
C1L02_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L02 = C1L02_p1_out # C1L02_p2_out # C1L02_p3_out;


--C1L61 is Data_Out_Mux:inst1|data_out[3]~4442 at LC39
C1L61_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L61_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L32;
C1L61_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L61 = C1L61_p1_out # C1L61_p2_out # C1L61_p3_out;


--C1L21 is Data_Out_Mux:inst1|data_out[2]~4446 at LC52
C1L21_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L21_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L42;
C1L21_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L21 = C1L21_p1_out # C1L21_p2_out # C1L21_p3_out;


--C1L4 is Data_Out_Mux:inst1|data_out[0]~4450 at LC20
C1L4_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L4_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L62;
C1L4_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L4 = C1L4_p1_out # C1L4_p2_out # C1L4_p3_out;


--C1L8 is Data_Out_Mux:inst1|data_out[1]~4454 at LC71
C1L8_p1_out = WR_N & B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L8_p2_out = B1_data_trs & !RD_N & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & A1L52;
C1L8_p3_out = WR_N & B1_data_trs & !RD_N & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3];
C1L8 = C1L8_p1_out # C1L8_p2_out # C1L8_p3_out;


--C1L23 is Data_Out_Mux:inst1|data_out[7]~4458 at LC10
C1L23_p1_out = A1L91 & E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L23_p2_out = A1L91 & !E1_reg_en[0] & E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N;
C1L23_p3_out = E1_reg_en[0] & !E1_reg_en[1] & !E1_reg_en[2] & !E1_reg_en[3] & B1_data_trs & !RD_N & WR_N;
C1L23 = C1L23_p1_out # C1L23_p2_out # C1L23_p3_out;


--PSEN_N is PSEN_N at PIN_5
--operation mode is input

PSEN_N = INPUT();


--ALE_E is ALE_E at PIN_83
--operation mode is input

ALE_E = INPUT();


--reset is reset at PIN_1
--operation mode is input

reset = INPUT();


--clk is clk at PIN_2
--operation mode is input

clk = INPUT();


--WR_N is WR_N at PIN_81
--operation mode is input

WR_N = INPUT();


--RD_N is RD_N at PIN_4
--operation mode is input

RD_N = INPUT();


--addr[15] is addr[15] at PIN_80
--operation mode is input

addr[15] = INPUT();


--addr[14] is addr[14] at PIN_79
--operation mode is input

addr[14] = INPUT();


--addr[13] is addr[13] at PIN_58
--operation mode is input

addr[13] = INPUT();


--addr[12] is addr[12] at PIN_9
--operation mode is input

addr[12] = INPUT();


--addr[11] is addr[11] at PIN_76
--operation mode is input

addr[11] = INPUT();


--addr[10] is addr[10] at PIN_75
--operation mode is input

addr[10] = INPUT();


--addr[9] is addr[9] at PIN_74
--operation mode is input

addr[9] = INPUT();


--addr[8] is addr[8] at PIN_73
--operation mode is input

addr[8] = INPUT();


--A1L91 is addr_data~0 at PIN_12
--operation mode is bidir

A1L91 = addr_data[7];

--addr_data[7] is addr_data[7] at PIN_12
--operation mode is bidir

addr_data[7]_tri_out = TRI(C1L92, B1_data_oe);
addr_data[7] = BIDIR(addr_data[7]_tri_out);


--A1L02 is addr_data~1 at PIN_11
--operation mode is bidir

A1L02 = addr_data[6];

--addr_data[6] is addr_data[6] at PIN_11
--operation mode is bidir

addr_data[6]_tri_out = TRI(C1L52, B1_data_oe);
addr_data[6] = BIDIR(addr_data[6]_tri_out);


--A1L12 is addr_data~2 at PIN_30
--operation mode is bidir

A1L12 = addr_data[5];

--addr_data[5] is addr_data[5] at PIN_30
--operation mode is bidir

addr_data[5]_tri_out = TRI(C1L12, B1_data_oe);
addr_data[5] = BIDIR(addr_data[5]_tri_out);


--A1L22 is addr_data~3 at PIN_54
--operation mode is bidir

A1L22 = addr_data[4];

--addr_data[4] is addr_data[4] at PIN_54
--operation mode is bidir

addr_data[4]_tri_out = TRI(C1L71, B1_data_oe);
addr_data[4] = BIDIR(addr_data[4]_tri_out);