clock_time.vhd

本文件解压后clock_time.vhd采用编程环境maxplusII

library ieee;
use ieee.std_logic_1164.all;
package my_pkg is	
	component i60bcd  	
	port(interg : in integer range 0 to 9;--interger number
		one : out std_logic_vector(6 downto 0));--7_segments led display
	end component;	
end my_pkg;

--////////////////////////////////////////////////////////////--

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

entity i60bcd is 	
	port(interg : in integer range 0 to 9;--interger number
		one : out std_logic_vector(6 downto 0));--7_segments led display		
end i60bcd;
architecture arch of i60bcd is
begin 
	process(interg)
	begin 
		case interg is
			when 0=>one<="0111111";
			when 1=>one<="0000110";
			when 2=>one<="1011011";
			when 3=>one<="1001111";
			when 4=>one<="1100110";
			when 5=>one<="1101101";
			when 6=>one<="1111101";
			when 7=>one<="0000111";
			when 8=>one<="1111111";
			when 9=>one<="1101111";
			when others=> one<="1111001";--e for error display	
		end case;			
	end process;
end arch;
			
--************************************************************--

--************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.my_pkg.all;
										
entity clock_time is
	port(rst: in std_logic;--power reset to initialize
		clk: in std_logic;--system clock 1024hz	
		stop,ok:in std_logic;--keep pushing to declare stop setting		
		one_tune: in std_logic;--pushing button to tune seconds
		ten_tune: in std_logic;--pushing button to tune minutes	
		seg4: out std_logic_vector(6 downto 0);--display seconds and times
		p1,p2,p3,p4,dp,speaker,led_stop: out std_logic);--power for sec_one,sec_ten,min_one,min_ten
end clock_time;

architecture arch of clock_time is
	signal hz1,dp1:std_logic;--1 hz clock
	--normal display time	
	signal sec_one,sec_ten,stop_one,stop_ten:integer range 0 to 9;
	--chosen in 7-segments led format
	signal sec7_one,sec7_ten,stop7_one,stop7_ten: std_logic_vector(6 downto 0);
	--index for alarm or stop _watch status	
	signal count : integer range 0 to 255;
	signal sel : std_logic_vector(1 downto 0);
	
begin 
	process (clk,rst)
	begin 
	 	if rising_edge(clk) then
			count<=count+1;
			if count>=255 then hz1<='1';
						  else hz1<='0';
			end if;
		end if;					
		if rst='0' then sec_one<=0;sec_ten<=0;stop_one<=0;stop_ten<=0;speaker<='0';led_stop<='1';--over 60
		elsif rising_edge(hz1) then  
			if stop='0' and ok='1' then --setting
					if one_tune='0' then 
						if stop_one=9 then stop_one<=0;
									else stop_one<=stop_one+1;
						end if;
					end if;
					if ten_tune='0' then 
						if stop_ten=5 then stop_ten<=0;
									else stop_ten<=stop_ten+1;
						end if;
					end if;
			elsif stop='0' and ok='0' then --down counting
				if sec_ten=stop_ten and sec_one=stop_one then 
					speaker<='1';led_stop<='0';dp1<='1';
				else					
					if sec_one=9 then sec_one<=0;
							if sec_ten=5 then sec_ten<=0;
							else sec_ten<=sec_ten+1;
							end if;
					else sec_one<=sec_one+1;
					end if;
					dp1<=not dp1; 									
				end if;														
			end if;
		end if;
		dp<=dp1;
	end process;

output:block
begin 	
	u1:i60bcd port map(interg=>sec_one,one=>sec7_one);
	u2:i60bcd port map(interg=>sec_ten,one=>sec7_ten);
	u3:i60bcd port map(interg=>stop_one,one=>stop7_one);
	u4:i60bcd port map(interg=>stop_ten,one=>stop7_ten);
end block output;	
	
scan_display: block
begin
	process(clk,rst)
	begin
	if rst='0' then sel<="00";
		elsif rising_edge(clk) then
				sel<=sel+"01";
			case sel is 
				when "00"=>seg4<=sec7_one;
							p1<='1';p2<='1';p3<='1';p4<='0';
				when "01"=>seg4<=sec7_ten;
							p1<='1';p2<='1';p3<='0';p4<='1';
				when "10"=>seg4<=stop7_one;
							p1<='1';p2<='0';p3<='1';p4<='1';
				when "11"=>seg4<=stop7_ten;
							p1<='0';p2<='1';p3<='1';p4<='1';
				when others=>seg4<="1011111";
			end case;
		end if;			
	end process;
end block scan_display;		
	
end arch;