_primary.vhd

来自「采用verilog编写的串口通信程序」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity com_receive is
    port(
        reset           : in     vl_logic;
        ren             : in     vl_logic;
        clk16x          : in     vl_logic;
        rxd             : in     vl_logic;
        data_ready      : out    vl_logic;
        frame_error     : out    vl_logic;
        dout            : out    vl_logic_vector(7 downto 0)
    );
end com_receive;