📄 lightw.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 15 10:48:58 2005 " "Info: Processing started: Thu Sep 15 10:48:58 2005" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off lightW -c lightW --generate_functional_sim_netlist " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lightW -c lightW --generate_functional_sim_netlist" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-alfa " "Info: Found design unit 1: div-alfa" { } { { "div.vhd" "" { Text "F:/usb backup/lightW/div.vhd" 8 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" { } { { "div.vhd" "" { Text "F:/usb backup/lightW/div.vhd" 4 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "light.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file light.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 light-behv " "Info: Found design unit 1: light-behv" { } { { "light.vhd" "" { Text "F:/usb backup/lightW/light.vhd" 8 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 light " "Info: Found entity 1: light" { } { { "light.vhd" "" { Text "F:/usb backup/lightW/light.vhd" 4 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lightW.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lightW.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lightW " "Info: Found entity 1: lightW" { } { { "lightW.bdf" "" { Schematic "F:/usb backup/lightW/lightW.bdf" { } } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divid.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divid.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divid-beta " "Info: Found design unit 1: divid-beta" { } { { "divid.vhd" "" { Text "F:/usb backup/lightW/divid.vhd" 21 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "1 divid " "Info: Found entity 1: divid" { } { { "divid.vhd" "" { Text "F:/usb backup/lightW/divid.vhd" 4 -1 0 } } } 0} } { } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "light light inst1 " "Warning: Port \"light\" of type light and instance \"inst1\" is missing source signal" { } { { "lightW.bdf" "" { Schematic "F:/usb backup/lightW/lightW.bdf" { { 200 72 192 296 "inst1" "" } } } } } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "banner light.vhd(10) " "Warning: VHDL Signal Declaration warning at light.vhd(10): ignored default value for signal \"banner\"" { } { { "light.vhd" "" { Text "F:/usb backup/lightW/light.vhd" 10 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_VARIABLE_IS_IGNORED" "flag light.vhd(22) " "Warning: VHDL Variable Declaration warning at light.vhd(22): ignored initial value expression for variable \"flag\"" { } { { "light.vhd" "" { Text "F:/usb backup/lightW/light.vhd" 22 0 0 } } } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count div.vhd(18) " "Warning: VHDL Process Statement warning at div.vhd(18): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" { } { { "div.vhd" "" { Text "F:/usb backup/lightW/div.vhd" 18 0 0 } } } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "addcore.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" { } { { "altshift.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } } } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 w
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