mp3if.v

通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接

module mp3if(RESETN, CLK, SA9, SA8, SA7, IOWN, IORN, SD, SCK, SDI,
	GPSO_REQ, GPSO_SCKR, GPSO_DATA, rx_int, IIC_SCK, IIC_SDI,CS0,CS0N);

input RESETN, CLK, SA9, SA8, SA7, IOWN, IORN;
input CS0 ;
output CS0N ;
inout [7:0] SD;
output SCK, SDI;
input GPSO_REQ, GPSO_DATA;
output GPSO_SCKR;
output  rx_int;
//input IORN;
input IIC_SCK, IIC_SDI;

reg [2:0] count;
reg en_tx, en_tx1;
reg [7:0] tx_data;
reg [1:0] clkdiv;
wire sclk;
wire tx_data_rstn;
wire en_tx1_rstn;

reg [2:0] rclkdiv;
reg [2:0] rcount;
reg en_rx;
reg [7:0] rx_data;
wire rd;
reg rx_int;

wire clr_rx_int_rstn;
reg clr_rx_int, clr_rx_int1;

assign CS0N = ~CS0 ;

always @ (negedge RESETN or posedge CLK)
if(~RESETN)
	clkdiv <= 2'h0;
else if(clkdiv == 2'h2)
	clkdiv <= 2'h0;
else 
	clkdiv <= clkdiv + 2'h1;

always @ (negedge RESETN or posedge CLK)
if(~RESETN)
	count <= 3'h0;
else if((clkdiv == 2'b10) & en_tx)
	count <= count + 3'h1;

/*always @ (negedge RESETN or posedge IOWN)
if(~RESETN)
	tx_data <= 8'h00;
else if(SA9 & SA8 & SA7)
	tx_data <= SD;
*/
assign tx_data_rstn = RESETN & ~(SA9 & SA8 & SA7 & ~IOWN);

always @ (negedge sclk or negedge tx_data_rstn )
if(~tx_data_rstn)
	tx_data <= SD;
else
	tx_data <= {tx_data[6:0], 1'b0};


assign en_tx1_rstn = RESETN & ~(en_tx & en_tx1);

always @ (negedge en_tx1_rstn or posedge IOWN)
if(~en_tx1_rstn)
	en_tx1 <= 1'h0;
else if(~en_tx1 & SA9 & SA8 & SA7)
	en_tx1 <= 1;


always @ (negedge RESETN or posedge CLK )
if(~RESETN)
	en_tx <= 1'h0;
else if(en_tx1 & (clkdiv == 2'b10))
	en_tx <= 1'b1;
else if((count == 7) & (clkdiv == 2'b10))
	en_tx <= 0;

assign sclk = (en_tx & clkdiv[0]);
assign SCK = ~sclk;

/*assign SDI = ((count == 0) & tx_data[7]) | ((count == 1) & tx_data[6]) |
		((count == 2) & tx_data[5]) | ((count == 3) & tx_data[4]) |
		((count == 4) & tx_data[3]) | ((count == 5) & tx_data[2]) |
		((count == 6) & tx_data[1]) | ((count == 7) & tx_data[0]);*/
assign SDI = tx_data[7];

always @ (negedge RESETN or posedge CLK)
if(~RESETN)
	rclkdiv <= 3'h0;
else if(rclkdiv == 3'h5)
	rclkdiv <= 3'h0;
else 
	rclkdiv <= rclkdiv + 3'h1;

always @ (negedge RESETN or posedge CLK)
if(~RESETN)
	rcount <= 3'h0;
else if((rclkdiv == 3'b101) & en_rx)
	rcount <= rcount + 3'h1;

always @ (negedge RESETN or posedge CLK )
if(~RESETN)
	en_rx <= 1'h0;
else if (rx_int)
	en_rx <= 1'h0;
else if(~en_rx & GPSO_REQ & (rclkdiv == 3'b101))
	en_rx <= 1'b1;
else if((rcount == 7) & (rclkdiv == 3'b101))
	en_rx <= 0;

always @ (negedge RESETN or posedge CLK )
if(~RESETN)
	rx_int <= 1'h0;
else if(en_rx & (rcount == 7) & (rclkdiv == 3'b101))
	rx_int <= 1;
else if(clr_rx_int & (rclkdiv == 3'b101))
	rx_int <= 1'b0;

always @ (negedge GPSO_SCKR or negedge RESETN)
//always @ (posedge GPSO_SCKR or negedge RESETN)
if(~RESETN)
	rx_data <= 8'h00;
else
	rx_data <= {rx_data[6:0], GPSO_DATA};
//	rx_data <= {GPSO_DATA, rx_data[7:1]};

assign rd = (SA9 & SA8 & SA7 & ~IORN);

assign SD = rd ? rx_data : 8'hzz;

assign GPSO_SCKR = en_rx & rclkdiv[1];

assign clr_rx_int_rstn = RESETN & ~clr_rx_int1;

always @ (negedge clr_rx_int_rstn or posedge IORN)
if(~clr_rx_int_rstn)
	clr_rx_int <= 1'h0;
else if(~clr_rx_int & SA9 & SA8 & SA7)
	clr_rx_int <= 1;

always @ (negedge RESETN or posedge CLK )
if(~RESETN)
	clr_rx_int1 <= 1'h0;
else if(rclkdiv == 3'b101)
	clr_rx_int1 <= clr_rx_int;

endmodule