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📄 bcd_bin2.rpt

📁 扫描信号从C3 ~C0送入,信号依序为1000 ->0100 ->0010 -> 0001->1000 循环,当扫描信号为1000时,则扫描第0行中的四个按键. 扫描信号为01
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Device-Specific Information:                             c:\sheji\bcd_bin2.rpt
bcd_bin2

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      3     -    C    08        OR2                0    4    0    2  |LPM_ADD_SUB:261|addcore:adder|pcarry3
   -      7     -    C    22        OR2                0    3    0    2  |LPM_ADD_SUB:261|addcore:adder|pcarry4
   -      3     -    C    22        OR2                0    3    0    2  |LPM_ADD_SUB:261|addcore:adder|pcarry5
   -      7     -    C    24        OR2                0    3    0    1  |LPM_ADD_SUB:261|addcore:adder|pcarry6
   -      6     -    C    08        OR2                0    2    0    2  |LPM_ADD_SUB:261|addcore:adder|:170
   -      4     -    C    08        OR2                0    4    0    3  |LPM_ADD_SUB:261|addcore:adder|:171
   -      1     -    C    22        OR2                0    3    0    2  |LPM_ADD_SUB:261|addcore:adder|:172
   -      5     -    C    22        OR2                0    3    0    3  |LPM_ADD_SUB:261|addcore:adder|:173
   -      2     -    C    24        OR2                0    3    0    2  |LPM_ADD_SUB:261|addcore:adder|:174
   -      2     -    C    02        OR2                2    2    0    3  |LPM_ADD_SUB:285|addcore:adder|pcarry2
   -      1     -    C    08        OR2                1    2    0    1  |LPM_ADD_SUB:285|addcore:adder|pcarry3
   -      7     -    C    08        OR2                1    3    0    3  |LPM_ADD_SUB:285|addcore:adder|:115
   -      3     -    C    01       AND2                0    2    0    1  |LPM_ADD_SUB:285|addcore:adder|:119
   -      8     -    C    24        OR2    s           0    4    0    1  |LPM_ADD_SUB:285|addcore:adder|~169~1
   -      1     -    C    24        OR2                0    3    0    1  |LPM_ADD_SUB:285|addcore:adder|:169
   -      6     -    C    02        OR2    s           2    1    0    1  |LPM_ADD_SUB:285|addcore:adder|~179~1
   -      5     -    C    08        OR2                1    2    0    1  |LPM_ADD_SUB:285|addcore:adder|:180
   -      1     -    C    02        OR2                0    3    0    4  |LPM_ADD_SUB:334|addcore:adder|pcarry2
   -      1     -    C    05        OR2                0    4    0    2  |LPM_ADD_SUB:334|addcore:adder|pcarry5
   -      7     -    C    05       AND2                0    2    0    1  |LPM_ADD_SUB:334|addcore:adder|:129
   -      1     -    C    20       AND2                1    0    0    3  |LPM_MULT:237|multcore:mult_core|romout0_2
   -      1     -    C    10       AND2                1    0    0    2  |LPM_MULT:237|multcore:mult_core|romout0_3
   -      6     -    C    22       AND2                1    0    0    2  |LPM_MULT:237|multcore:mult_core|romout0_4
   -      4     -    C    22        OR2                3    0    0    2  |LPM_MULT:237|multcore:mult_core|romout0_6
   -      2     -    C    22        OR2                4    0    0    1  |LPM_MULT:237|multcore:mult_core|romout0_7
   -      8     -    C    22        OR2                2    0    0    2  |LPM_MULT:237|multcore:mult_core|:2249
   -      1     -    C    12       AND2                1    0    0    3  |LPM_MULT:246|multcore:mult_core|romout0_1
   -      1     -    C    21       AND2                1    0    0    3  |LPM_MULT:246|multcore:mult_core|romout0_2
   -      3     -    C    24        OR2                4    0    0    2  |LPM_MULT:246|multcore:mult_core|romout0_4
   -      6     -    C    24        OR2                4    0    0    1  |LPM_MULT:246|multcore:mult_core|romout0_7
   -      4     -    C    24        OR2                4    0    0    2  |LPM_MULT:246|multcore:mult_core|:1559
   -      5     -    C    24        OR2                4    0    0    2  |LPM_MULT:246|multcore:mult_core|:1562
   -      2     -    C    12        OR2                2    0    0    2  |LPM_MULT:246|multcore:mult_core|:1613
   -      6     -    C    01        OR2                1    1    0    1  :392
   -      5     -    C    01        OR2                1    2    0    1  :398
   -      3     -    C    05        OR2                1    2    0    1  :404
   -      2     -    C    05        OR2                1    2    0    1  :410
   -      8     -    C    08        OR2                1    1    0    1  :416
   -      7     -    C    02        OR2                1    2    0    1  :422
   -      4     -    C    02        OR2                2    1    0    1  :428
   -      1     -    C    07        OR2                2    0    0    1  :434
   -      8     -    C    01        OR2                1    1    0    1  :440
   -      7     -    C    01        OR2                1    1    0    2  :446
   -      5     -    C    05        OR2                1    1    0    2  :452
   -      4     -    C    05        OR2                1    1    0    3  :458
   -      2     -    C    08        OR2                1    1    0    4  :464
   -      8     -    C    02        OR2                1    1    0    2  :470
   -      5     -    C    02        OR2                1    1    0    3  :476
   -      4     -    C    07        OR2                1    1    0    4  :482
   -      2     -    C    01        OR2                1    3    1    0  :489
   -      4     -    C    01        OR2                1    2    1    0  :495
   -      6     -    C    05        OR2                1    3    1    0  :501
   -      8     -    C    05        OR2                1    3    1    0  :507
   -      1     -    C    01        OR2                1    2    1    0  :513
   -      3     -    C    02        OR2                1    3    1    0  :519
   -      5     -    C    07        OR2                1    2    1    0  :525
   -      7     -    C    07       AND2                1    1    1    0  :531


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                             c:\sheji\bcd_bin2.rpt
bcd_bin2

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     4/ 48(  8%)     0/ 48(  0%)    0/16(  0%)      4/16( 25%)     0/16(  0%)
C:      17/ 96( 17%)    14/ 48( 29%)    12/ 48( 25%)    1/16(  6%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                             c:\sheji\bcd_bin2.rpt
bcd_bin2

** EQUATIONS **

bd       : INPUT;
n0       : INPUT;
n1       : INPUT;
n2       : INPUT;
n3       : INPUT;
p0       : INPUT;
p1       : INPUT;
p2       : INPUT;
p3       : INPUT;
x0       : INPUT;
x1       : INPUT;
x2       : INPUT;
x3       : INPUT;

-- Node name is 'ab0' 
-- Equation name is 'ab0', type is output 
ab0      =  _LC7_C7;

-- Node name is 'ab1' 
-- Equation name is 'ab1', type is output 
ab1      =  _LC5_C7;

-- Node name is 'ab2' 
-- Equation name is 'ab2', type is output 
ab2      =  _LC3_C2;

-- Node name is 'ab3' 
-- Equation name is 'ab3', type is output 
ab3      =  _LC1_C1;

-- Node name is 'ab4' 
-- Equation name is 'ab4', type is output 
ab4      =  _LC8_C5;

-- Node name is 'ab5' 
-- Equation name is 'ab5', type is output 
ab5      =  _LC6_C5;

-- Node name is 'ab6' 
-- Equation name is 'ab6', type is output 
ab6      =  _LC4_C1;

-- Node name is 'ab7' 
-- Equation name is 'ab7', type is output 
ab7      =  _LC2_C1;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C8', type is buried 
_LC3_C8  = LCELL( _EQ001);
  _EQ001 =  _LC1_C10 &  _LC2_C12
         #  _LC1_C10 &  _LC1_C20 &  _LC1_C21
         #  _LC1_C20 &  _LC1_C21 &  _LC2_C12;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ002);
  _EQ002 =  _LC3_C8 &  _LC6_C22
         #  _LC3_C8 &  _LC3_C24
         #  _LC3_C24 &  _LC6_C22;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ003);
  _EQ003 =  _LC7_C22 &  _LC8_C22
         #  _LC4_C24 &  _LC7_C22
         #  _LC4_C24 &  _LC8_C22;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_C24', type is buried 
_LC7_C24 = LCELL( _EQ004);
  _EQ004 =  _LC3_C22 &  _LC4_C22
         #  _LC3_C22 &  _LC5_C24
         #  _LC4_C22 &  _LC5_C24;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|:170' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_C8', type is buried 
_LC6_C8  = LCELL( _EQ005);
  _EQ005 = !_LC1_C20 &  _LC1_C21
         #  _LC1_C20 & !_LC1_C21;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|:171' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_C8', type is buried 
_LC4_C8  = LCELL( _EQ006);
  _EQ006 =  _LC1_C10 &  _LC1_C20 &  _LC1_C21 &  _LC2_C12
         # !_LC1_C10 &  _LC1_C20 &  _LC1_C21 & !_LC2_C12
         #  _LC1_C10 & !_LC1_C21 & !_LC2_C12
         #  _LC1_C10 & !_LC1_C20 & !_LC2_C12
         # !_LC1_C10 & !_LC1_C21 &  _LC2_C12
         # !_LC1_C10 & !_LC1_C20 &  _LC2_C12;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|:172' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ007);
  _EQ007 =  _LC3_C8 &  _LC3_C24 &  _LC6_C22
         #  _LC3_C8 & !_LC3_C24 & !_LC6_C22
         # !_LC3_C8 & !_LC3_C24 &  _LC6_C22
         # !_LC3_C8 &  _LC3_C24 & !_LC6_C22;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|:173' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = LCELL( _EQ008);
  _EQ008 =  _LC4_C24 &  _LC7_C22 &  _LC8_C22
         # !_LC4_C24 &  _LC7_C22 & !_LC8_C22
         # !_LC4_C24 & !_LC7_C22 &  _LC8_C22
         #  _LC4_C24 & !_LC7_C22 & !_LC8_C22;

-- Node name is '|LPM_ADD_SUB:261|addcore:adder|:174' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_C24', type is buried 
_LC2_C24 = LCELL( _EQ009);
  _EQ009 =  _LC3_C22 &  _LC4_C22 &  _LC5_C24
         #  _LC3_C22 & !_LC4_C22 & !_LC5_C24
         # !_LC3_C22 &  _LC4_C22 & !_LC5_C24
         # !_LC3_C22 & !_LC4_C22 &  _LC5_C24;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C2', type is buried 
_LC2_C2  = LCELL( _EQ010);
  _EQ010 =  _LC6_C8 &  x2
         #  _LC1_C12 &  _LC6_C8 &  x1
         #  _LC1_C12 &  x1 &  x2;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = LCELL( _EQ011);
  _EQ011 =  _LC2_C2 &  _LC4_C8
         #  _LC2_C2 &  x3
         #  _LC4_C8 &  x3;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C8', type is buried 
_LC7_C8  = LCELL( _EQ012);
  _EQ012 =  _LC1_C22 &  _LC2_C2 &  _LC4_C8
         #  _LC1_C22 &  _LC2_C2 &  x3
         #  _LC1_C22 &  _LC4_C8 &  x3;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = LCELL( _EQ013);
  _EQ013 =  _LC5_C22 &  _LC7_C8;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|~169~1' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C24', type is buried 
-- synthesized logic cell 
_LC8_C24 = LCELL( _EQ014);
  _EQ014 =  _LC2_C24 &  _LC5_C22 &  _LC7_C8 & !_LC7_C24
         # !_LC7_C8 &  _LC7_C24
         # !_LC5_C22 &  _LC7_C24
         # !_LC2_C24 &  _LC7_C24;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|:169' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C24', type is buried 
_LC1_C24 = LCELL( _EQ015);
  _EQ015 =  _LC2_C22 &  _LC6_C24 &  _LC8_C24
         # !_LC2_C22 & !_LC6_C24 &  _LC8_C24
         # !_LC2_C22 &  _LC6_C24 & !_LC8_C24
         #  _LC2_C22 & !_LC6_C24 & !_LC8_C24;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|~179~1' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_C2', type is buried 
-- synthesized logic cell 
_LC6_C2  = LCELL( _EQ016);
  _EQ016 = !_LC1_C12 &  x2
         # !x1 &  x2
         #  _LC1_C12 &  x1 & !x2;

-- Node name is '|LPM_ADD_SUB:285|addcore:adder|:180' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = LCELL( _EQ017);
  _EQ017 =  _LC2_C2 &  _LC4_C8 &  x3
         #  _LC2_C2 & !_LC4_C8 & !x3
         # !_LC2_C2 &  _LC4_C8 & !x3
         # !_LC2_C2 & !_LC4_C8 &  x3;

-- Node name is '|LPM_ADD_SUB:334|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ018);
  _EQ018 =  _LC4_C7
         #  _LC5_C2
         #  _LC8_C2;

-- Node name is '|LPM_ADD_SUB:334|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = LCELL( _EQ019);
  _EQ019 =  _LC1_C2 &  _LC2_C8
         #  _LC4_C5
         #  _LC5_C5;

-- Node name is '|LPM_ADD_SUB:334|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ020);
  _EQ020 =  _LC1_C2 &  _LC2_C8;

-- Node name is '|LPM_MULT:237|multcore:mult_core|romout0_2' from file "multcore.tdf" line 676, column 33
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = LCELL( n0);

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