bcd_bin2.vhd

来自「扫描信号从C3 ～C0送入,信号依序为1000 ->0100 ->0」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bcd_bin2 IS
PORT(bd:IN STD_LOGIC;
    n,p,x:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ab:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END bcd_bin2;
ARCHITECTURE rtl OF bcd_bin2 IS
SIGNAL b:INTEGER RANGE 0 TO 200;
SIGNAL cd: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS (bd,n,p,x,b)
BEGIN
IF (bd='1') THEN
b<=CONV_INTEGER(n)*100+CONV_INTEGER(p)*10+CONV_INTEGER(x);
cd<=CONV_STD_LOGIC_VECTOR(b,8);
ab<=cd + "000110111";--输出连8至位D/A转换器输入端
ELSE
ab<="00000000";
END IF;
END PROCESS;
END rtl;