ddsall.vhd

DDS的vhdl语言源程序实现 该程序可实现1HZ频率步进

library ieee;
use ieee.std_logic_1164.all;
entity ddsall is
    port(  bclk  : in std_logic;         -- 系统时钟
           ddsout  : out std_logic_vector(7 downto 0);-- DDS输出 
           P0:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
           CS:IN STD_LOGIC;
           RD,WR:IN STD_LOGIC;
           ALE:IN STD_LOGIC;
           AD_CS:OUT STD_LOGIC;
           READY:IN STD_LOGIC;
           outclk:out std_logic;
           DATAIN1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          LATCH1:IN STD_LOGIC);
 end ddsall;

architecture behave of ddsall is
  component ddsc is                           -- DDS主模块
        port( bclk  : in std_logic;         -- DDS合成时钟
             freqin : in std_logic_vector (19 downto 0);-- 频率字输入
             outclk: out std_logic; 
            ddsout:out std_logic_vector(7 downto 0));-- DDS输出
    end component ddsc;

component MCS_51  is                                        --接口例化说明
   port(P0:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); 
        CS:IN STD_LOGIC;
        RD,WR:IN STD_LOGIC;
        ALE:IN STD_LOGIC;
        AD_CS:OUT STD_LOGIC;
        READY:IN STD_LOGIC;
        DATAIN1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        LATCH1:IN STD_LOGIC;
        DATOUT3:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        DATOUT1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        DATOUT2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end component MCS_51;

    signal  freqind : std_logic_vector(19 downto 0);  -- 频率字 
begin
   U0:  MCS_51 port map(P0=>P0,CS=>CS,RD=>RD,WR=>WR,ALE=>ALE,READY=>READY,
        AD_CS=>AD_CS,DATAIN1=>DATAIN1,LATCH1=>LATCH1,
        DATOUT1=>freqind(7 downto 0),DATOUT2=>freqind(15 downto 8),
         DATOUT3=>freqind(19 DOWNTO 16));

    i_ddsc  : ddsc      -- 例化DDSC
        port map(bclk => bclk,freqin => freqind,outclk=>outclk,ddsout => ddsout );
        
end behave;