mkey_in.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

use ieee.std_logic_arith.all ;

entity MKEY_IN is
  port (
	KEY_BUF: out std_logic_vector(15 downto 0);
    KEY_SEL : out std_logic_vector(3 downto 0);		-- Key select
	KEY_IN :  in  std_logic_vector(3 downto 0);		-- Key input
    CLK :     in  std_logic							-- Sampling Clock
     );
end MKEY_IN;

architecture arch_MKEY_IN of MKEY_IN is

--signal KEY_BUF: std_logic_vector(15 downto 0);		-- key input buffer
signal KEY_CNT: std_logic_vector(1 downto 0);

begin

process(CLK)
begin
	if (CLK'event and CLK = '0') then
		KEY_CNT <= KEY_CNT + 1;	
	  	case KEY_CNT(1 downto 0) is 
			when "00" =>   KEY_SEL <= "0001" ;
			when "01" =>   KEY_SEL <= "0010" ;
			when "10" =>   KEY_SEL <= "0100" ;
			when others => KEY_SEL <= "1000" ;
		end case ;
    end if;
    if (CLK'event and CLK = '1') then
	  	case KEY_CNT(1 downto 0) is 
			when "00" =>   KEY_BUF(3 downto 0) <= KEY_IN ;
			when "01" =>   KEY_BUF(7 downto 4) <= KEY_IN ;
			when "10" =>   KEY_BUF(11 downto 8) <= KEY_IN ;
			when others => KEY_BUF(15 downto 12) <= KEY_IN ;
		end case ;
	end if ;
end process;

end arch_MKEY_IN;