pcic.v

DesignWave 2005 8 Verilog Example

module PCIC (
	pc104_a ,pc104_d ,pc104_d_out ,pc104_smemw_n ,pc104_smemr_n ,pc104_iow_n ,
	pc104_ior_n ,pc104_reset_drv ,pc104_sysclk ,pc104_sbhe_n ,pc104_iochrdy_n ,
	pc104_irq3_n ,pc104_irq4_n ,pc104_irq5_n ,pc104_irq6_n ,pc104_irq7_n ,
	pc_wait_n ,pc_ireq_n ,pc_cd_n ,bus_en_req ,bus_en_n ,pc_ce1_n ,
	pc_ce2_n ,pc_we_n ,pc_oe_n ,pc_iord_n ,pc_iowr_n ,pc_reg_n ,
	pc_reset ,pc_a ,databuff_245_dir ,databuff_245_oe_n ,card_on_off
) ;

input	[23:0]	pc104_a ;
input	[7:0]	pc104_d ;
inout		pc104_d_out ;
input		pc104_smemw_n ;
input		pc104_smemr_n ;
input		pc104_iow_n ;
input		pc104_ior_n ;
input		pc104_reset_drv ;
input		pc104_sysclk ;
input		pc104_sbhe_n ;
output		pc104_iochrdy_n ;
output		pc104_irq3_n ;
output		pc104_irq4_n ;
output		pc104_irq5_n ;
output		pc104_irq6_n ;
output		pc104_irq7_n ;
input		pc_wait_n ;
input		pc_ireq_n ;
input		pc_cd_n ;
input		bus_en_req ;
output		bus_en_n ;
inout		pc_ce1_n ;
inout		pc_ce2_n ;
inout		pc_we_n ;
inout		pc_oe_n ;
inout		pc_iord_n ;
inout		pc_iowr_n ;
inout		pc_reg_n ;
inout		pc_reset ;
output	[8:0]	pc_a ;
output		databuff_245_dir ;
output		databuff_245_oe_n ;
output		card_on_off ;

reg	[4:0]	index_register ;
reg		card_on_off ;
reg		pc_card_reset ;
reg	[2:0]	irq_number ;
reg		io_windows ;
reg	[4:0]	window0start_lo ;
reg	[1:0]	window0start_hi ;
reg	[4:0]	window0stop_lo ;
reg	[1:0]	window0stop_hi ;
reg		reg_active ;
reg	[8:0]	card_offset ;

//**************************************************
//************ ADDRESS 3E0 3E1 DECOODER ************
//**************************************************
wire index_register_decood = ( pc104_a[9:0] == 10'b11_1110_0000 ) ; // ADDRESS 3E0
wire data_register_decood = ( pc104_a[9:0] == 10'b11_1110_0001 ) ;  // ADDRESS 3E1


//**************************************************
//************ ADDRESS 3E0 3E1 DATA LATCH **********
//**************************************************
//wire reg_clr = pc104_reset_drv | pc_cd_n ;
wire reg_clr = pc104_reset_drv ;
always @(posedge pc104_iow_n or posedge reg_clr ) begin
if ( reg_clr ) begin
	index_register[4:0] <= 0 ;
	card_on_off <= 0 ;
	pc_card_reset <= 1 ;
	irq_number[2:0] <= 0 ;
	io_windows <= 0 ;
	window0start_lo[4:0] <= 0 ;
	window0start_hi[1:0] <= 0 ;
	window0stop_lo[4:0] <= 0 ;
	window0stop_hi[1:0] <= 0 ;
	reg_active <= 1 ;
	card_offset[8:0] <= 0 ;
end
else begin
//INDEX REGISTER
	index_register[4:0] <= ( index_register_decood ) ? pc104_d[4:0]  : index_register ;
//POWER AND RESETDRV
	card_on_off <= ( data_register_decood &  ( index_register == 5'h02 )) ? pc104_d[4] : card_on_off ; //030724
//INTERRUPT AND GENERAL CONTROL
	pc_card_reset <= ( data_register_decood &  ( index_register == 5'h03 )) ? pc104_d[6] : pc_card_reset ;
	irq_number[2:0] <= ( data_register_decood &  ( index_register == 5'h03 )) ? pc104_d[2:0] : irq_number ;
//ADDRES WINDOW ENABLE
	io_windows <= ( data_register_decood &  ( index_register == 5'h06 )) ? pc104_d[6] : io_windows ;
//IO ADDRESSMAPPING START STOP
	window0start_lo[4:0] <= ( data_register_decood &  ( index_register == 5'h08 )) ? pc104_d[7:3] : window0start_lo ;
	window0start_hi[1:0] <= ( data_register_decood &  ( index_register == 5'h09 )) ? pc104_d[1:0] : window0start_hi ;
	window0stop_lo[4:0] <= ( data_register_decood &  ( index_register == 5'h0a )) ? pc104_d[7:3] : window0stop_lo ;
	window0stop_hi[1:0] <= ( data_register_decood &  ( index_register == 5'h0b )) ? pc104_d[1:0] : window0stop_hi ;
	reg_active <= ( data_register_decood &  ( index_register == 5'h15 )) ? pc104_d[6] : reg_active ;
//PC CARD MEM ADDRESS = { WINDOW ADDRESS 9BIT(019h=0C8h) , ISA ADDRESS 15 BIT } + CARD MEMORY OFFSET ADDRESS[25:15] )
//CARD MEMORY OFFSET ADDRESS[19:15]
	card_offset[4:0] <= ( data_register_decood &  ( index_register == 5'h14 )) ? pc104_d[7:3] : card_offset[4:0] ;
//CARD MEMORY OFFSET ADDRESS[25:20]
	card_offset[8:5] <= ( data_register_decood &  ( index_register == 5'h15 )) ? pc104_d[3:0] : card_offset[8:5] ;
end
end


//**************************************************
//************ OUTPUT DATA ENABLE ******************
//**************************************************
wire pc104_oe = data_register_decood & ~pc104_ior_n ;
assign pc104_d_out = ( pc104_oe )? ~pc_cd_n : 1'bz ;


//**************************************************
//************ PC104 => PC CARD  *******************
//**************************************************

// MEMRY EREA ADDRESS WINDOW 0x0C8
wire mem_window_comp = ( pc104_a[23:15] == 9'b000011010 ) ;  // ISA 0x0C8h ( 23:15 = 019h)

wire io_window_comp_sta_hi = ( window0start_hi == pc104_a[9:8] ) ;
wire io_window_comp_sta_lo = ( window0start_lo <= pc104_a[7:3] ) ;
wire io_window_comp_stp_hi = ( window0stop_hi == pc104_a[9:8] ) ;
wire io_window_comp_stp_lo = ( window0stop_lo >= pc104_a[7:3] ) ;

wire io_window_comp = io_window_comp_sta_hi & io_window_comp_sta_lo & io_window_comp_stp_hi & io_window_comp_stp_lo ;

wire pc_ce1_w_n = ~((( ~pc104_smemw_n | ~pc104_smemr_n ) & mem_window_comp )
                    | (( ~pc104_iow_n | ~pc104_ior_n ) & io_window_comp & io_windows )) ;

assign pc_ce1_n = ( ~bus_en_req )? pc_ce1_w_n : 1'bz ;
assign pc_ce2_n = ( ~bus_en_req )? ~( ~pc_ce1_w_n  & ~pc104_sbhe_n ) : 1'bz ;
assign pc_we_n = ( ~bus_en_req )? ~( ~pc_ce1_w_n  & ~pc104_smemw_n ) : 1'bz ;
assign pc_oe_n = ( ~bus_en_req )? ~( ~pc_ce1_w_n  & ~pc104_smemr_n ) : 1'bz ;
assign pc_iord_n = ( ~bus_en_req )? ~( ~pc_ce1_w_n  & ~pc104_ior_n ) : 1'bz ;
assign pc_iowr_n = ( ~bus_en_req )? ~( ~pc_ce1_w_n  & ~pc104_iow_n ) : 1'bz ;
assign pc_reg_n = ( ~bus_en_req )? ~(( ~pc_ce1_w_n  & reg_active ) | ~pc_iowr_n | ~pc_iowr_n ) : 1'bz ;
assign pc_reset = ( ~bus_en_req )? ~pc_card_reset | pc104_reset_drv : 1'bz ;


assign pc_a[8:0] = ( bus_en_req )? 9'bzzzzzzzzz : ( ~pc_iord_n | ~pc_iowr_n )? 0 : card_offset[8:0] ;
                     

//**************************************************
//************ PC CARD => PC104  *******************
//**************************************************
assign pc104_iochrdy_n = ( ~pc_wait_n & io_window_comp & ~bus_en_req )? 1'b0 : 1'bz ;
assign pc104_irq3_n = (( irq_number == 3 ) & ~bus_en_req & ~pc_ireq_n )? 1 : 0 ;
assign pc104_irq4_n = (( irq_number == 4 ) & ~bus_en_req & ~pc_ireq_n )? 1 : 0 ;
assign pc104_irq5_n = (( irq_number == 5 ) & ~bus_en_req & ~pc_ireq_n )? 1 : 0 ;
assign pc104_irq6_n = (( irq_number == 6 ) & ~bus_en_req & ~pc_ireq_n )? 1 : 0 ;
assign pc104_irq7_n = (( irq_number == 7 ) & ~bus_en_req & ~pc_ireq_n )? 1 : 0 ;

//**************************************************
//************ DATA BAS CONTROL(LVC245) ************
//**************************************************

assign databuff_245_dir = ( pc104_smemr_n & pc104_ior_n ) | bus_en_req ;
assign databuff_245_oe_n = ~( ~pc_ce1_w_n & ~bus_en_req ) ;
assign bus_en_n = bus_en_req ;

endmodule