t_regi2csm.vhd~

DesignWave 2005 8 Verilog Example

						wait for PERIOD * SLAVEDELAY ;
						wait until rising_edge(CLK) ;
						WriteRData(slvData) ;
						SlaveMessageString <= "SRdData:* " ;
						SlaveMessageValue <= slvData ;
						MessageRec ;
						MessageTrReg ;
					when X"5E" | X"65" =>
						MessageWriteRData ;
						MessageTrReg ;
						slvData := unsigned(slvData) + 1 ;
						MessageStatus ;
						MessageWriteRData ;
						MessageTrReg ;
					when others =>
						MessageWriteRData ;
				end case ;
				slvData := unsigned(slvData) + 1 ;
			elsif SWrData(4) = '1' then
				if slvWrDelay = '1' then
					wait for PERIOD * SLAVEDELAY ;
					wait until rising_edge(CLK) ;
				end if ;
				ReadWData ;
				MessageData ;
				case SwrData is
					when X"36" =>
						WriteWData ;
						slvWrDelay := '0' ;
					when X"24" =>
						slvWrDelay := '1' ;
					when others =>
						slvWrDelay := '0' ;
				end case ;
			end if ;
			MessageStatus ;
		end loop ;
	end process ;
		
--	SrdDataGen: process(CLK, nRST)
--	begin
--		if nRST = '0' then
--			SrdData <= "11001101" ;
--			SrdCntr0 <= "010110" ;
--		elsif rising_edge(CLK) then
--			if SrdDReq = '1' and SrdDRdy = '1' then
--				SrdData(7 downto 1) <= SrdData(6 downto 0) ;
--				SrdData(0) <= not SrdData(7) ;
--				SrdCntr0(4 downto 0) <= SrdCntr0(5 downto 1) ;
--				SrdCntr0(5) <= '0' ;
--			end if ;
--		end if ;
--	end process ;



-- for Mater Unit
	MasterStim: process
		
		procedure RegWrite(ADRS : in std_logic_vector(2 downto 0) ; DATA : in std_logic_vector(7 downto 0)) is
		begin
			MUsel <= '1' ;
			MUadrs <= ADRS ;
			MWrEn <= '1' ;
			MDin <= DATA ;
			wait until rising_edge(CLK) ;
			MWrEn <= '0' ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure RegRead(ADRS : in std_logic_vector(2 downto 0)) is
		begin
			MUsel <= '1' ;
			MUadrs <= ADRS ;
			MRdEn <= '1' ;
			wait until rising_edge(CLK) ;
			MRdData <= MDout ;
			MRdEn <= '0' ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure GetStatus is
		begin
			RegRead("000") ;
		end procedure ;

		procedure WriteCmnd(WCD : in std_logic_vector(7 downto 0)) is
		begin
			RegWrite("000", WCD) ;
		end procedure ;

		procedure ReadWData is
		begin
			RegRead("011") ;
		end procedure ;

		procedure WriteWData(WDD : in std_logic_vector(7 downto 0)) is
		begin
			RegWrite("011", WDD) ;
		end procedure ;

		procedure ReadRData is
		begin
			RegRead("010") ;
		end procedure ;

		procedure WriteRData is
		begin
			RegWrite("010", "00000000") ;
		end procedure ;

		procedure GetTrReg is
		begin
			RegRead("111") ;
		end procedure ;

		procedure WaitFor(WDD : in integer) is
		begin
			wait for PERIOD * 8 ;
			wait until rising_edge(CLK) ;
		end procedure ;

		procedure MessageRec is
		begin
			MasterMessageReq <= '1' ;
			wait until MasterMessageAck = '1' ;
			MasterMessageReq <= '0' ;
			wait until MasterMessageAck = '0' ;
		end procedure ;

		procedure MessageTrReg is
		begin
			GetTrReg ;
			MasterMessageString <= "TrReg :   " ;
			MasterMessageValue <= MRdData ;
			MessageRec ;
		end procedure ;

		procedure MessageStatus is
		begin
			GetStatus ;
			MasterMessageString <= "Status:   " ;
			MasterMessageValue <= MRdData ;
			MessageRec ;
		end procedure ;

		procedure MessageInt is
		begin
			MasterMessageString <= "MInt:OK   " ;
			MasterMessageValue <= (others => '0') ;
			MessageRec ;
		end procedure ;

		procedure MessageString(STR : in string(1 to MessageLength)) is
		begin
			MasterMessageString <= STR ;
			MasterMessageValue <= (others => '0') ;
			MessageRec ;
		end procedure ;

		procedure MessageWaitIntnReport is
		begin
			wait until MInt = '1' ;
			MessageInt ;

			MessageTrReg ;
			MessageStatus ;
		end procedure ;
			
		procedure MessageData is
		begin
			MasterMessageString <= "MRdData:  " ;
			MasterMessageValue <= MRdData ;
			MessageRec ;
		end procedure ;

	begin
		MRdData <= (others => '0') ;
		mstData <= "10000001" ;
		MSimCode <= 0 ;
		MWrEn <= '0' ;
		MRdEn <= '0' ;
		MUsel <= '0' ;
		MUadrs <= (others => '0') ;
		MDin <= (others => '0') ;
		wait until nRST = '1' and rising_edge(CLK) ;
		wait until rising_edge(CLK) ;

		RegWrite("100", "00110001") ;  	-- Spos = 3, Spre = 1
		RegWrite("101", "01011001") ;  	-- Thig = 5, Tlow = 9
		RegWrite("110", "00000001") ;  	-- Dhol = 1
		RegWrite("111", "00000001") ;  	-- Int Enable
		
		wait until SlaveUnitReady = '1' ;

-- (1) Invalid Address Call
		MSimCode <= 1 ;
		MessageString("*InvAdrs *") ;
		RegWrite("001", "01110001") ;--		RegWrite("001", "00010111") ;
		WriteCmnd("00000001") ;

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;

-- (2) Write 4 data
		MSimCode <= 2 ;
		MessageString("*Wr4Data1*") ;
		RegWrite("001", "00010111") ;
		WriteCmnd("00000000") ;

		MessageWaitIntnReport ;

		WriteWData("10100101") ;  		-- Write Data = A5h
		MessageTrReg ;
		WriteWData("01011010") ;  		-- Write Data = 5Ah
		MessageTrReg ;

		MessageWaitIntnReport ;

		WriteWData("11000011") ;  		-- Write Data = C3h
		MessageTrReg ;

		MessageWaitIntnReport ;
		
		ReadWData ;  					-- Term
		WriteWData("00111100") ;  		-- Write Data = 3Ch
		MessageTrReg ;

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;

-- (3) Write 1 datum /w CONT
		MSimCode <= 3 ;
		MessageString("*Wr1Data1*") ;
		--RegWrite("001", "00010111") ;
		WriteCmnd("00000010") ;

		ReadWData ;  					-- Term
		WriteWData("00001001") ;  		-- Write Data = 09h

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;

-- (4) Write 1 datum
		MSimCode <= 4 ;
		MessageString("*Wr1Data2*") ;
		WriteCmnd("00000000") ;

		ReadWData ;  					-- Term

		MessageWaitIntnReport ;

		WriteWData("00100000") ;  		-- Write Data = 20h
		MessageTrReg ;

		MessageWaitIntnReport ;

-- (5) Write 2 data x2
		MSimCode <= 5 ;
		MessageString("*Wr2DDbl *") ;
		WriteCmnd("00000010") ;  		-- CONT for the first tr.
		WriteCmnd("00000000") ;  		-- the second tr.
		MessageStatus ;
		WriteCmnd("00000100") ;  		-- the third tr. to be ignored
		MessageStatus ;

		WriteWData("00011001") ;  		-- Write Data = 19h
		MessageTrReg ;

		ReadWData ;  					-- Term to be ignored

		MessageWaitIntnReport ;

		ReadWData ;  					-- Term

		MessageWaitIntnReport ;

		wait for PERIOD * 32 ;
		wait until rising_edge(CLK) ;

		WriteWData("01110110") ;  		-- Write Data = 76h
		MessageTrReg ;

		WriteWData("01011001") ;  		-- Write Data = 59h
		MessageTrReg ;

		ReadWData ;  					-- Term
		MessageWaitIntnReport ;  		-- Wait for the first tr. to end

		MessageWaitIntnReport ;

		ReadWData ;  					-- Term
		WriteWData("01001000") ;  		-- Write Data = 48h
		MessageTrReg ;

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;

-- (6) Read 4 data
		MSimCode <= 6 ;
		MessageString("*Rd4Data *") ;
		WriteCmnd("00000001") ;

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The first data should be 59h
		MessageTrReg ;

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The second data should be 5Ah

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The third data should be 5Ch

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;  		-- The forth data should be 5Dh
		ReadRData ;
		MessageData ;

		MessageWaitIntnReport ;

-- (7) Read 1 datum /w CONT
		MSimCode <= 7 ;
		MessageString("*Rd1Data1*") ;
		WriteCmnd("00000011") ;  		-- CONT(+)

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The first data should be 5Eh
		--MessageTrReg ;

		MessageWaitIntnReport ;

-- (8) Read 1 datum
		MSimCode <= 8 ;
		MessageString("*Rd1Data2*") ;
		WriteCmnd("00000001") ;  		-- CONT(+)

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The first data should be 5Fh
		--MessageTrReg ;

		MessageWaitIntnReport ;

-- (9) Read 2 data x2
		MSimCode <= 9 ;
		MessageString("*Rd2Data *") ;
		WriteCmnd("00000011") ;  		-- CONT(+)
		WriteCmnd("00000001") ;  		-- the second tr.
		MessageStatus ;
		WriteCmnd("00000100") ;  		-- the third tr. to be ignored
		MessageStatus ;

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					-- The first data should be 61h
		--MessageTrReg ;

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;
		wait for PERIOD * MASTERDELAY ;  		-- Data Read Delay
		wait until rising_edge(CLK) ;
		ReadRData ;
		MessageData ;  					-- The second data should be 62h

		MessageWaitIntnReport ;

		MessageWaitIntnReport ;
		wait for PERIOD * MASTERDELAY ;
		wait until rising_edge(CLK) ;
		ReadRData ;
		MessageData ;  					-- The first data should be 63h

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;
		ReadRData ;
		MessageData ;  					--	The Second data should be 64h

		MessageWaitIntnReport ;

-- (10) Read after Write (Write 4 data / Read 4 data)
		MSimCode <= 10 ;
		MessageString("* Rd/Wr1 *") ;
		WriteCmnd("00000010") ;  		-- CONT(+)
		WriteCmnd("00000001") ;  		-- the second tr.
		MessageStatus ;

		WriteWData("00100001") ;  		-- Write Data = 21h
		MessageTrReg ;
		
		MessageWaitIntnReport ;

		WriteWData("01000011") ;  		-- Write Data = 43h
		MessageTrReg ;

		MessageWaitIntnReport ;

		MessageWaitIntnReport ;

		WriteWData("01100101") ;  		-- Write Data = 65h
		MessageTrReg ;

		ReadWData ;  					-- Term
		
		WriteWData("10000111") ;  		-- Write Data = 87h
		MessageTrReg ;

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;

		-- Read
		for i in 0 to 2 loop
			MessageWaitIntnReport ;  	-- Data should be  65h, 66h, 68h
			ReadRData ;
			MessageData ;
		end loop ;

		WriteRData ;  					-- Term

		MessageWaitIntnReport ;  		-- Data should be 69h
		wait for PERIOD * MASTERDELAY ;
		wait until rising_edge(CLK) ;
		ReadRData ;
		MessageData ;

		MessageWaitIntnReport ;


-- (11) Write 4 data
		MSimCode <= 11 ;
		MessageString("*Wr4Data2*") ;
		RegWrite("001", "00010111") ;
		WriteCmnd("00000000") ;

		--MessageWaitIntnReport ;

		WriteWData("00010011") ;  		-- Write Data = 13h
		MessageTrReg ;

		MessageWaitIntnReport ;

		WriteWData("00100100") ;  		-- Write Data = 24h
		MessageTrReg ;

		MessageWaitIntnReport ;

		WriteWData("00110110") ;  		-- Write Data = 36h
		MessageTrReg ;

		MessageWaitIntnReport ;

		WriteWData("01000111") ;  		-- Write Data = 47h
		MessageTrReg ;

		MessageWaitIntnReport ;

		WriteWData("01011000") ;  		-- Write Data = 58h
		MessageTrReg ;

		for i in 0 to 1 loop
			MessageWaitIntnReport ;
		end loop ;


-- (11) Write 4 data
		MSimCode <= 12 ;
		MessageString("*StrtByte*") ;
		WriteCmnd("00000100") ;
		MessageTrReg ;
		MessageStatus ;

		MessageWaitIntnReport ;

--		wait for PERIOD * 64 ;
--		assert FALSE
--			report "Simulation Complete."
--			severity FAILURE ;
		wait ;
	end process ;


end stimulus ;