simrecord.ref.txt

DesignWave 2005 8 Verilog Example

[Master] *InvAdrs *00
[Master] MInt:OK   00
[Master] TrReg :   81
[Master] Status:   88
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   08
[Master] *Wr4Data1*00
[Master] MInt:OK   00
[Master] TrReg :   25
[Master] Status:   80
[Master] TrReg :   01
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  A5
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  5A
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  C3
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  3C
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Wr1Data1*00
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   22
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  09
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Wr1Data2*00
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   02
[Master] MInt:OK   00
[Master] TrReg :   25
[Master] Status:   80
[Master] TrReg :   01
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  20
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Wr2DDbl *00
[Master] Status:   C0
[Master] Status:   C0
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   22
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   C0
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  19
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   25
[Master] Status:   C0
[Master] TrReg :   01
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  76
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   49
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   02
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  59
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   1B
[Slave]  SWrData:  48
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Rd4Data *00
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   22
[Slave]  SInt:OK   00
[Slave]  TrReg :   21
[Slave]  SRdData:  5A
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  59
[Master] TrReg :   01
[Slave]  SInt:OK   00
[Slave]  TrReg :   21
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  5A
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  5C
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  5C
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:* 5D
[Slave]  TrReg :   01
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  5D
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Rd1Data1*00
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   22
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  5E
[Slave]  TrReg :   01
[Slave]  Status:   80
[Slave]  SRdData:  5F
[Slave]  TrReg :   09
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  5E
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Rd1Data2*00
[Slave]  SInt:OK   00
[Slave]  TrReg :   89
[Slave]  Status:   02
[Slave]  SInt:OK   00
[Slave]  TrReg :   21
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  5F
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Rd2Data *00
[Master] Status:   C0
[Master] Status:   C0
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   22
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  61
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   C0
[Master] MRdData:  61
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  62
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   C0
[Master] MRdData:  62
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   02
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  63
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  64
[Slave]  Status:   80
[Master] MRdData:  63
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  64
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] * Rd/Wr1 *00
[Master] Status:   C0
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   22
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   C0
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  21
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   C0
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  43
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   25
[Master] Status:   C0
[Master] TrReg :   01
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  65
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   C0
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  87
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   02
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:  65
[Slave]  TrReg :   01
[Slave]  Status:   80
[Slave]  SRdData:  66
[Slave]  TrReg :   09
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  65
[Slave]  SInt:OK   00
[Slave]  TrReg :   21
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  66
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:* 68
[Slave]  TrReg :   01
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  68
[Slave]  SInt:OK   00
[Slave]  TrReg :   25
[Slave]  SRdData:* 69
[Slave]  TrReg :   01
[Slave]  Status:   80
[Master] MInt:OK   00
[Master] TrReg :   13
[Master] Status:   80
[Master] MRdData:  69
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00
[Master] *Wr4Data2*00
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   22
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  13
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  24
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Master] MInt:OK   00
[Master] TrReg :   21
[Master] Status:   80
[Master] TrReg :   09
[Slave]  SWrData:  36
[Slave]  Status:   40
[Slave]  SInt:OK   00
[Slave]  TrReg :   13
[Slave]  SWrData:  47
[Slave]  Status:   40
[Master] MInt:OK   00
[Master] TrReg :   81
[Master] Status:   84
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   04
[Master] *StrtByte*00
[Master] TrReg :   01
[Master] Status:   80
[Slave]  SInt:OK   00
[Slave]  TrReg :   81
[Slave]  Status:   22
[Master] MInt:OK   00
[Master] TrReg :   41
[Master] Status:   00