readme.sjis.txt

DesignWave 2005 8 Verilog Example

i2c僐儞僩儘乕儔  / 0.5.0c

丒僼傽僀儖峔惉
 regI2cMaster.vhd (0.5.0c) : Master儌僕儏乕儖杮懱+儗僕僗僞丒僀儞僞乕僼僃乕僗
 +-- rif_i2cMaster.vhd (0.5.0c) : Master儌僕儏乕儖梡儗僕僗僞丒僀儞僞乕僼僃乕僗
 +-- i2cMaster.vhd (0.5.1c) : Mastr儌僕儏乕儖杮懱
     +-- i2cMAU/i2cDrv.vhd (0.5.0c) : i2c僶僗僪儔僀僶(SCL/SDA惗惉)

 regI2cSlave.vhd  (0.5.0c) : Slave儌僕儏乕儖杮懱+儗僕僗僞丒僀儞僞乕僼僃乕僗
 +-- rif_i2cSlave.vhd (0.5.0c) : Slave儌僕儏乕儖梡儗僕僗僞丒僀儞僞乕僼僃乕僗
 +-- i2cSlave.vhd (0.5.0c) : Slave儌僕儏乕儖杮懱

     +-- i2cBasics_package.vhd (0.5.0c) : 嫟捠儌僕儏乕儖偺僷僢働乕僕
     +-- i2cStDec.vhd (0.5.0c) : i2cMaster/i2cSlave梡偺嫟捠儌僕儏乕儖
         |                       (i2c偺僶僗丒僗僥乕僩傪専弌)
         +-- i2cMAU/i2cRcv.vhd (0.5.0c) : i2c僶僗偺揮憲梫慺傪専弌

丒僥僗僩丒儌僕儏乕儖 verif/t_regI2cSM.vhd (0.1.1c)
丂regI2cMaster/regI2cSlave梡僔儈儏儗乕僞丒僥僗僩儀儞僠丅
  2偮偺儌僕儏乕儖娫偱12庬椶偺揮憲僷僞乕儞傪幚峴丄儘僌傪"SimRecord.txt"偵婰榐偡
傞丅惓忢摦嶌帪偺儕僼傽儗儞僗偑"SimRecord.ref.txt"丅栺1.5msec丅


T. Kohno (www.digicat.info)