i2crcv.vhd

DesignWave 2005 8 Verilog Example

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-- i2cRrv (i2c receiver)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c  / 27, May., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
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library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity i2cRcv is
	port(	CLK, nRST, syncRST	: in std_logic ;
			CKE					: in std_logic ;  -- CLK enable for sampling clock
			
			-- i2c Bus
			SCL, SDA			: in std_logic ;
			
			-- i2cRcv I/F
			BoSCH				: out std_logic ;
			EoSCH				: out std_logic ;
			STAC				: out std_logic ;
			STPC				: out std_logic ;
			vSCL				: out std_logic ;
			vSDA				: out std_logic
			) ;
end i2cRcv ;


architecture RTL of i2cRcv is

type i2cRcvState is (rcvPOR, rcvSCLH, rcvSCLL) ;
signal RQ								: i2cRcvState ;

signal rSCL0, rSCL1, rSCL2, eSCL, ivSCL		: std_logic ;
signal rSDA0, rSDA1, rSDA2, eSDA, ivSDA		: std_logic ;
signal redgeSCL, fedgeSCL					: std_logic ;
signal redgeSDA, fedgeSDA					: std_logic ;


begin

	-- Root Sequencer for i2cRcv
	i2cRcvRootSeq: process(CLK, nRST)
	begin
		if nRST = '0' then
			RQ <= rcvPOR ;
		elsif rising_edge(CLK) then
			if syncRST = '1' then
				RQ <= rcvPOR ;
			else
				case RQ is
					when rcvPOR =>
						if ivSCL = '1' then
							RQ <= rcvSCLH ;
						end if ;
					when rcvSCLH =>
						if fedgeSCL = '1' then
							RQ <= rcvSCLL ;
						end if ;
					when rcvSCLL =>
						if redgeSCL = '1' then
							RQ <= rcvSCLH ;
						end if ;
					when others =>
						RQ <= rcvPOR ;
				end case ;
			end if ;
		end if ;
	end process ;



	-- SCL Sampler
	SCLSampler: process(CLK, nRST)
	begin
		if nRST = '0' then
			rSCL0 <= '1' ;
			rSCL1 <= '1' ;
		elsif rising_edge(CLK) then
			if syncRST = '1' then
				rSCL0 <= '1' ;
				rSCL1 <= '1' ;
			elsif CKE = '1' then
				rSCL0 <= SCL ;
				rSCL1 <= rSCL0 ;
			end if ;
		end if ;
	end process ;

	rSCL2loader: process(CLK, nRST)
	begin
		if nRST = '0' then
			rSCL2 <= '1' ;
		elsif rising_edge(CLK) then
			if syncRST = '1' then
				rSCL2 <= '1' ;
			elsif eSCL = '1' then
				rSCL2 <= rSCL1 ;
			end if ;
		end if ;
	end process ;

	eSCL <= '1' when rSCL0 = rSCL1 else
			'0' ;
	ivSCL <= rSCL1 when eSCL = '1' else
			 rSCL2 ;

	-- SDA Sampler
	SDASampler: process(CLK, nRST)
	begin
		if nRST = '0' then
			rSDA0 <= '1' ;
			rSDA1 <= '1' ;
		elsif rising_edge(CLK) then
			if syncRST = '1' then
				rSDA0 <= '1' ;
				rSDA1 <= '1' ;
			elsif CKE = '1' then
				rSDA0 <= SDA ;
				rSDA1 <= rSDA0 ;
			end if ;
		end if ;
	end process ;

	vSDAloader: process(CLK, nRST)
	begin
		if nRST = '0' then
			rSDA2 <= '1' ;
		elsif rising_edge(CLK) then
			if syncRST = '1' then
				rSDA2 <= '1' ;
			elsif eSDA = '1' then
				rSDA2 <= rSDA1 ;
			end if ;
		end if ;
	end process ;

	eSDA <= '1' when rSDA0 = rSDA1 else
			'0' ;
	ivSDA <= rSDA1 when eSCL = '1' else
			 rSDA2 ;


	-- rising_edge and falling_edge detector
	redgeSCL <= '1' when rSCL1 = '1' and rSCL2 = '0' and eSCL = '1' else
				'0' ;
	fedgeSCL <= '1' when rSCL1 = '0' and rSCL2 = '1' and eSCL = '1' else
				'0' ;

	redgeSDA <= '1' when rSDA1 = '1' and rSDA2 = '0' and eSDA = '1' else
				'0' ;
	fedgeSDA <= '1' when rSDA1 = '0' and rSDA2 = '1' and eSDA = '1' else
				'0' ;


	-- Output signals
	BoSCH <= redgeSCL when RQ /= rcvPOR else
			 '0' ;
	EoSCH <= fedgeSCL ;
	STAC <= '1' when fedgeSDA = '1' and RQ = rcvSCLH and ivSCL = '1' else
			'0' ;
	STPC <= '1' when redgeSDA = '1' and RQ = rcvSCLH and ivSCL = '1' else
			'0' ;
	vSCL <= ivSCL ;
	vSDA <= ivSDA ;



end RTL ;