adctes.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

use ieee.std_logic_arith.all ;

entity ADCTES is port (
	clkin	: in std_logic ; 	-- CLK IN
	rst		: in std_logic ;	-- reset
	ad_clk 	: out std_logic ;	-- ADC clock out
	ad_cs	: out std_logic ;	-- ADC cs
	ad_dout	: in std_logic ;	-- ADC data out
	ad_din	: out std_logic ;	-- ADC data in
    rbuf    : out std_logic_vector( 11 downto 0)
	) ;
end ADCTES ;

architecture arch_ADCTES of ADCTES is

signal sbuf	: std_logic_vector( 19 downto 0) ;	-- Send Buffer
--signal rbuf : std_logic_vector( 19 downto 0) ;	-- Recive Buffer
-- signal rst	: std_logic ;
signal wcnt	: std_logic_vector(4 downto 0);

begin

ad_clk <= clkin;

process (clkin, rst)
begin
  if rst = '0' then
    ad_cs <= '1' ;
    sbuf <= "01100100000000000000";   -- set ADC CH.1
    wcnt <= "00000" ;	 
  elsif ( clkin'event and clkin = '1' ) then
    wcnt <= wcnt + 1;
    if (wcnt = "10100") then
      wcnt <= "00000";
      rbuf(11 downto 0) <= sbuf(11 downto 0);
      ad_cs <= '1' ;
      sbuf <= "01100100000000000000";	-- set ADC CH.1
    else
      ad_cs <= '0' ; 
      sbuf(19 downto 1) <= sbuf( 18 downto 0);	-- send Command
      ad_din <= sbuf(19);
      sbuf(0) <= ad_dout;
    end if ;
  end if ;
end process ;

end arch_ADCTES;