vramif.vhd

DesignWave 2005 8 Verilog Example

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-- VRamIF (VRam Reader for MDPGen)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c  / 9, Jun., 2005
--
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--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
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library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;

--use WORK.i2cCommon.all ;

entity VRamIF is
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- MDPGen I/F
			DIReq				: in std_logic ;  -- Request strobe for DotInt
			BKRep				: in std_logic ;
			DotInt				: out std_logic_vector(63 downto 0) ;  -- Dot Intensity 8bits x 8
			
			-- Configurations
			VRHead				: in std_logic_vector(5 downto 0) ;
			VRTail				: in std_logic_vector(5 downto 0) ;
			VRWrp				: in std_logic
			) ;
end VRamIF ;



architecture RTL of VRamIF is

constant RamDataWaitCntrWidth		: integer := 3 ;
constant RamWordWidth				: integer := 64 / (2 ** VBDIV) ;
constant RamAdrsWidth				: integer := 6 ;

signal RamAdrsCntr		: std_logic_vector(RamAdrsWidth - 1 downto 0) ;
signal efRamAdrs		: std_logic_vector(RamAdrsWidth - 1 downto 0) ;
signal wrRamAdrs		: std_logic_vector(RamAdrsWidth - 1 downto 0) ;
signal RamAdrsTail		: std_logic ;  	-- '1' when RamAdrsCntr is equal to regVRTail
signal RamAdrsWrpd		: std_logic ;  	-- '1' when RamAdrsCntr has exceeded regVRTail once

signal RamAdrsLowCntr	: std_logic_vector(2 downto 0) ;  -- counts word address in a column
signal ROutComp			: std_logic ;

signal RamDataRdy		: std_logic ;
signal RamDataWaitCntr	: std_logic_vector(RamDataWaitCntrWidth - 1 downto 0) ;

signal regRamData		: std_logic_vector(63 downto 0) ;
signal DataMask			: std_logic ;

signal regVRHead		: std_logic_vector(5 downto 0) ;
signal regVRTail		: std_logic_vector(5 downto 0) ;
signal regVRWrp			: std_logic ;

type VRamIFState	is (Idle, Conf, ROut) ;
signal RQ				: VRamIFState ;


begin

-- Ram I/F
	RamRdEn <= '1' when RQ = ROut else
			   '0' ;
	RamAdrs(VBDIV + 5 downto VBDIV) <= RamAdrsCntr ;
	LowAdrs: if VBDIV > 0 generate
		RamAdrs(VBDIV -1 downto 0) <= RamAdrsLowCntr(VBDIV - 1 downto 0) ;
	end generate ;
	DotInt <= regRamData when DataMask = '0' else
			  (others => '0') ;
	


-- Root Seq.
	VRamIFRootSeq: process(CLK, nRST)
	begin
		if nRST = '0' then
			RQ <= Idle ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				RQ <= Idle ;
			else
				case RQ is
					when Idle =>
						if BKRep = '1' then
							RQ <= conf ;
						elsif DIReq = '1' then
							RQ <= ROut ;
						end if ;
					when conf =>
						RQ <= ROut ;
					when ROut =>
						if ROutComp = '1' and RamDataRdy = '1' then
							RQ <= Idle ;
						end if ;
					when others =>
				end case ;
			end if ;
		end if ;
	end process ;



-- RamAdrs generator
	-- generates Effective Column Address (RamAdrsBase)
	RamAdrsBaseGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			RamAdrsCntr <= (others => '0') ;
			RamAdrsWrpd <= '0' ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				RamAdrsCntr <= (others => '0') ;
				RamAdrsWrpd <= '0' ;
			else
				case RQ is
					when Idle =>
						if DIReq = '1' then
							if RamAdrsTail = '1' then
								RamAdrsCntr <= regVRHead ;
								RamAdrsWrpd <= '1' ;
							elsif regVRWrp = '1' or RamAdrsWrpd = '0' then
								RamAdrsCntr <= unsigned(RamAdrsCntr) + 1 ;
							end if ;
						end if ;
					when Conf =>
						RamAdrsCntr <= regVRHead ;
						RamAdrsWrpd <= '0' ;
					when others =>
				end case ;
			end if ;
		end if ;
	end process ;

	RamAdrsTail <= '1' when RamAdrsCntr = regVRTail else
				   '0' ;
	DataMask <= '1' when RamAdrsWrpd = '1' and regVRWrp = '0' else
				'0' ;

	-- generates word address in a column
	RamAdrsLowCounter: process(CLK, nRST)
	begin
		if nRST = '0' then
			RamAdrsLowCntr <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				RamAdrsLowCntr <= (others => '0') ;
			elsif RQ = ROut then
				if RamDataRdy = '1' then
					RamAdrsLowCntr <= unsigned(RamAdrsLowCntr) + 1 ;
				end if ;
			else
				RamAdrsLowCntr <= (others => '0') ;
			end if ;
		end if ;
	end process ;

	ROutComp <= '1' when RamAdrsLowCntr = CONV_STD_LOGIC_VECTOR(2 ** VBDIV - 1, 3) else
				'0' ;



	-- generates wait timing for ram data read out
	RamReadTimingGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			RamDataWaitCntr <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				RamDataWaitCntr <= (others => '0') ;
			else
				if RQ = ROut and RamDataRdy = '0' then
					RamDataWaitCntr <= unsigned(RamDataWaitCntr) + 1 ;
				else
					RamDataWaitCntr <= (others => '0') ;
				end if ;
			end if ;
		end if ;
	end process ;

	RamDataRdy <= '1' when RamDataWaitCntr = CONV_STD_LOGIC_VECTOR(RAMWAIT, RamDataWaitCntrWidth) else
				  '0' ;



-- Ram Data Loader
	RDL: process(CLK, nRST)
	begin
		if nRST = '0' then
			regRamData <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				regRamData <= (others => '0') ;
			else
				if RamDataRdy = '1' then
					regRamData(63 downto 64 - RamWordWidth) <= RamData ;
					for i in 0 to 2 ** VBDIV - 2 loop
						regRamData((i + 1 ) * RamWordWidth - 1 downto i * RamWordWidth)	<=
							regRamData((i + 2) * RamWordWidth - 1 downto (i + 1) * RamWordWIdth) ;
					end loop ;
				end if ;
			end if ;
		end if ;
	end process ;



-- Configuration regs.
	ConfRegs: process(CLK, nRST)
	begin
		if nRST = '0' then
			regVRHead <= (others => '0') ;
			regVRTail <= (others => '0') ;
			regVRWrp <= '0' ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				regVRHead <= (others => '0') ;
				regVRTail <= (others => '0') ;
				regVRWrp <= '0' ;
			else
				if BKRep = '1' then
					regVRHead <= VRHead ;
					regVRTail <= VRTail ;
					regVRWrp <= VRWrp ;
				end if ;
			end if ;
		end if ;
	end process ;
					
				



end RTL ;