rif_dmtxdrv.vhd

DesignWave 2005 8 Verilog Example

--------------------------------------------------------------------------------
-- rif_DMtxDrv.vhd (Register I/F for DMtxDrv)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c  / 11, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity rif_DMtxDrv is
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;

			nsyncRST			: out std_logic ;
			-- for MDPGen
			CurCol				: in std_logic_vector(4 downto 0) ;
			Blnk				: in std_logic ;
			CLKDiv				: out std_logic_vector(11 downto 0) ;
			Col2Row				: out std_logic_vector(11 downto 0) ;  -- Row data load latency
			BLCnt				: out std_logic_vector(1 downto 0) ; -- Blank cols. a scan
			-- for VRamIF
			VRHead				: out std_logic_vector(5 downto 0) ;
			VRTail				: out std_logic_vector(5 downto 0) ;
			VRWrp				: out std_logic
			) ;
end rif_DMtxDrv ;



architecture RTL of rif_DMtxDrv is

constant ClkDivWidth	: integer := 12 ;
constant BLCntWidth		: integer := 2 ;
constant RamAdrsWidth	: integer := 6 ;
constant CurColWidth	: integer := 5 ;

-- Register addresses
constant ADRS_CLKDIVLOW		: std_logic_vector(2 downto 0) := "000" ;
constant ADRS_CLKDIVHIGH	: std_logic_vector(2 downto 0) := "001" ;
constant ADRS_COL2ROWLOW	: std_logic_vector(2 downto 0) := "010" ;
constant ADRS_COL2ROWHIGH	: std_logic_vector(2 downto 0) := "011" ;
constant ADRS_BLCNT			: std_logic_vector(2 downto 0) := "100" ;
constant ADRS_VRHEAD		: std_logic_vector(2 downto 0) := "101" ;
constant ADRS_VRTAIL		: std_logic_vector(2 downto 0) := "110" ;
constant ADRS_VRCTRL		: std_logic_vector(2 downto 0) := "111" ;

-- Register select signals
signal rselClkDivLow		: std_logic ;
signal rselClkDivHigh		: std_logic ;
signal rselCol2RowLow		: std_logic ;
signal rselCol2RowHigh		: std_logic ;
signal rselBLCnt			: std_logic ;
signal rselVRHead			: std_logic ;
signal rselVRTail			: std_logic ;
signal rselVRCtrl			: std_logic ;

-- Registers
signal regClkDiv			: std_logic_vector(ClkDivWidth - 1 downto 0) ;
signal regCol2Row			: std_logic_vector(ClkDivWidth - 1 downto 0) ;
signal regBLCnt				: std_logic_vector(BLCntWidth - 1 downto 0) ;
signal regVRHead			: std_logic_vector(RamAdrsWidth - 1 downto 0) ;
signal regVRTail			: std_logic_vector(RamAdrsWidth - 1 downto 0) ;
signal regVRWrp				: std_logic ;
signal regEnable			: std_logic ;


begin

-- Register select signals
	rselClkDivLow <= Usel when Uadrs = ADRS_CLKDIVLOW else
					 '0' ;
	rselClkDivHigh <= Usel when Uadrs = ADRS_CLKDIVHIGH else
					  '0' ;
	rselCol2RowLow <= Usel when Uadrs = ADRS_COL2ROWLOW else
					  '0' ;
	rselCol2RowHigh <= Usel when Uadrs = ADRS_COL2ROWHIGH else
					   '0' ;
	rselBLCnt <= Usel when Uadrs = ADRS_BLCNT else
				 '0' ;
	rselVRHead <= Usel when Uadrs = ADRS_VRHEAD else
				  '0' ;
	rselVRTail <= Usel when Uadrs = ADRS_VRTAIL else
				  '0' ;
	rselVRCtrl <= Usel when Uadrs = ADRS_VRCTRL else
				  '0' ;

-- Register I/F output
	with Uadrs select
		Dout <= regClkDiv(7 downto 0) when ADRS_CLKDIVLOW,
				EXT(regClkDiv(ClkDivWidth - 1 downto 8), 8) when ADRS_CLKDIVHIGH,
				regCol2Row(7 downto 0) when ADRS_COL2ROWLOW,
				EXT(regCol2Row(ClkDivWidth - 1 downto 8), 8) when ADRS_COL2ROWHIGH,
				EXT(regBLCnt, 8) when ADRS_BLCNT,
				EXT(regVRHead, 8) when ADRS_VRHEAD,
				EXT(regVRTail, 8) when ADRS_VRTAIL,
				(regEnable & regVRWrp & Blnk & CurCol) when ADRS_VRCTRL,
				(others => '0') when others ;



---------------------------------------------------------------------------------------------------
-- Display timing configuration registers
---------------------------------------------------------------------------------------------------
	DisplayTimings: process(CLK, nRST)
	begin
		if nRST = '0' then
			regClkDiv <= (others => '0') ;
			regCol2Row <= (others => '0') ;
			regBLCnt <= (others => '0') ;
		elsif rising_edge(CLK) then
			if WrEn = '1' then
				if rselClkDivLow = '1' then
					regClkDiv(7 downto 0) <= Din ;
				end if ;
				if rselClkDivHigh = '1' then
					regClkDiv(ClkDivWidth - 1 downto 8) <= Din(ClkDivWidth - 9 downto 0) ;
				end if ;
				if rselCol2RowLow = '1' then
					regCol2Row(7 downto 0) <= Din ;
				end if ;
				if rselCol2RowHigh = '1' then
					regCol2Row(ClkDivWidth - 1 downto 8) <= Din(ClkDivWidth - 9 downto 0) ;
				end if ;
				if rselBLCnt = '1' then
					regBLCnt <= Din(BLCntWidth - 1 downto 0) ;
				end if ;
			end if ;
		end if ;
	end process ;



---------------------------------------------------------------------------------------------------
-- Display area configuration registers
---------------------------------------------------------------------------------------------------
	DisplayAreas: process(CLK, nRST)
	begin
		if nRST = '0' then
			regVRHead <= (others => '0') ;
			regVRTail <= (others => '0') ;
			regVRWrp <= '0' ;
			regEnable <= '0' ;
		elsif rising_edge(CLK) then
			if WrEn = '1' then
				if rselVRHead = '1' then
					regVRHead <= Din(RamAdrsWidth - 1 downto 0) ;
				end if ;
				if rselVRTail = '1' then
					regVRTail <= Din(RamAdrsWidth - 1 downto 0) ;
				end if ;
				if rselVRCtrl = '1' then
					regVRWrp <= Din(6) ;
					regEnable <= Din(7) ;
				end if ;
			end if ;
		end if ;
	end process ;

	nsyncRST <= regEnable ;



---------------------------------------------------------------------------------------------------
-- Configuration output
---------------------------------------------------------------------------------------------------
	-- for MDPGen
	CLKDiv <= regCLKDiv ;
	Col2Row <= regCol2Row ;
	BLCnt <= regBLCnt ;
	-- for VRamIF
	VRHead <= regVRHead ;
	VRTail <= regVRTail ;
	VRWrp <= regVRWrp ;



end RTL ;