mdpgen.vhd

DesignWave 2005 8 Verilog Example

--------------------------------------------------------------------------------
-- MDPGen (Matrix Drive Pattern Generator)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c  / 9, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity MDPGen is
	generic ( COLSIZE			: integer := 3
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0) ;

			-- Row data generator I/F
			DIReq				: out std_logic ;  -- Request strobe for DotInt
			BKRep				: out std_logic ;  -- Blank Column report
			DotInt				: in std_logic_vector(63 downto 0) ;  -- Dot Intensity 8bits x 8
			
			-- Configurations / Status
			ColNo				: out std_logic_vector(4 downto 0) ;
			Blnk				: out std_logic ;
			CLKDiv				: in std_logic_vector(11 downto 0) ;
			Col2Row				: in std_logic_vector(11 downto 0) ;  -- Row data load latency
			BLCnt				: in std_logic_vector(1 downto 0)  -- Blank cols. a scan
			) ;
end MDPGen ;


architecture RTL of MDPGen is

constant ZERO12			: std_logic_vector(11 downto 0) := "000000000000" ;

signal DivCKECntr		: std_logic_vector(11 downto 0) ;  -- counter for DivCLK / CLK ratio
signal DivCKECntrZERO	: std_logic ;
signal DivCKE			: std_logic ;

signal DivCntr			: std_logic_vector(3 downto 0) ;  -- counter for ColCLK / DivCLK ratio
signal DivCntrZERO		: std_logic ;
signal DivCntrFULL		: std_logic ;
signal cBlnk, ColEn		: std_logic ;
signal dColEn			: std_logic ;

signal ColCntr			: std_logic_vector(4 downto 0) ;
signal ColCntrFULL		: std_logic ;
signal vBlnkCntr		: std_logic_vector(1 downto 0) ;
signal nvBlnk			: std_logic ;

signal preLoad_drvRow	: std_logic ;

type drvRowCntrArray is array (0 to 7) of std_logic_vector(3 downto 0) ;
signal drvRowCntr0, drvRowCntr1			: drvRowCntrArray ;


begin

-- Dot Intensity Data Reader I/F
	DIReqGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			DIReq <= '0' ;
			dColEn <= '0' ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				DIReq <= '0' ;
				dColEn <= '0' ;
			else
				DIReq <= ColEn and (nvBlnk and not ColCntrFULL) ;
				dColEn <= ColEn ;
			end if ;
		end if ;
	end process ;

	BKRep <= dColEn when nvBlnk = '1' and ColCntr = "00000" else
			 '0' ;
	ColNo <= ColCntr ;


---------------------------------------------------------------------------------------------------
-- Central Pattern Generator ;)
---------------------------------------------------------------------------------------------------

-- Clock divider
	-- generates DivCKE, the base clock enable for matrix drive signals
	DivCKEGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			DivCKECntr <= (others => '0') ;
			DivCKE <= '0' ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				DivCKECntr <= (others => '0') ;
				DivCKE <= '0' ;
			else
				if DivCKECntrZERO = '1' then
					DivCKECntr <= CLKDiv ;
					DivCKE <= '1' ;
				else
					DivCKECntr <= unsigned(DivCKECntr) - 1 ;
					DivCKE <= '0' ;
				end if ;
			end if ;
		end if ;
	end process ;
				
	DivCKECntrZERO <= '1' when DivCKECntr = ZERO12 else
					  '0' ;


-- ncBlnk & ColEn generator
	-- generates ncBlnk, the base clock enable for columns
	cBlnkGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			DivCntr <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				DivCntr <= (others => '0') ;
			elsif DivCKE = '1' then
				DivCntr <= unsigned(DivCntr) + 1 ;
			end if ;
		end if ;
	end process ;

	DivCntrZERO <= '1' when DivCntr = "0000" else
				   '0' ;
	DivCntrFULL <= '1' when DivCntr = "1111" else
				   '0' ;
	cBlnk <= DivCntrFULL and DivCKE ;
	ColEn <= DivCntrZERO and DivCKE ;


-- Column Number and nvBlnk generator
	-- Sequencer
	ColCntrGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			ColCntr <= (others => '0') ;
			nvBlnk <= '0' ;
			vBlnkCntr <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				ColCntr <= (others => '0') ;
				nvBlnk <= '0' ;
				vBlnkCntr <= (others => '0') ;
			elsif ColEn = '1' then
				if nvBlnk = '1' then
					vBlnkCntr <= BLCnt ;
					if ColCntrFULL = '1' then
						ColCntr <= (others => '0') ;
						if vBlnkCntr /= "00" then
							nvBlnk <= '0' ;
						end if ;
					else
						ColCntr <= unsigned(ColCntr) + 1 ;
					end if ;
				else
					ColCntr <= (others => '0') ;
					vBlnkCntr <= unsigned(vBlnkCntr) - 1 ;
					if vBlnkCntr(1) = '0' then
						nvBlnk <= '1' ;
					end if ;
				end if ;
			end if ;
		end if ;
	end process ;

	ColCntrFULL <= '1' when ColCntr(4 downto 3) = CONV_STD_LOGIC_VECTOR(COLSIZE - 1, 2) and ColCntr(2 downto 0) = "111" else
				   '0' ;



---------------------------------------------------------------------------------------------------
-- Dots (a column) Generator
---------------------------------------------------------------------------------------------------
-- drvCol generator
	-- decodes ColCntr(4 downto 0) to drvCol(COLSIZE * 8 - 1 downto 0)
	drvColGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			drvCol <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				drvCol <= (others => '0') ;
			else
				if cBlnk = '1' then
					drvCol <= (others => '0') ;
				elsif ColEn = '1' and nvBlnk = '1' then
					drvColDecode: for i in COLSIZE * 8 - 1 downto 0 loop
						if i = unsigned(ColCntr) then
							drvCol(i) <= '1' ;
						else
							drvCol(i) <= '0' ;
						end if ;
					end loop ;
				end if ;
				
			end if ;
		end if ;
	end process ;

	-- Blnk report generator
	Blnk <= not nvBlnk ;


-- drvRow generator
	-- counts drvRow drive length
	drvRowCounters: process(CLK, nRST)
	begin
		if nRST = '0' then
			for i in 0 to 7 loop
				drvRowCntr0(i) <= (others => '0') ;
				drvRowCntr1(i) <= (others => '0') ;
			end loop ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				for i in 0 to 7 loop
					drvRowCntr0(i) <= (others => '0') ;
					drvRowCntr1(i) <= (others => '0') ;
				end loop ;
			else
				if cBlnk = '1' then
					for i in 0 to 7 loop
						drvRowCntr0(i) <= DotInt(i * 8 + 3 downto i * 8) ;
						drvRowCntr1(i) <= DotInt(i * 8 + 7 downto i * 8 + 4) ;
					end loop ;
				elsif DivCKE = '1' then
					for i in 0 to 7 loop
						if drvRowCntr0(i) /= "0000" then
							drvRowCntr0(i) <= unsigned(drvRowCntr0(i)) - 1 ;
						end if ;
						if drvRowCntr1(i) /= "0000" then
							drvRowCntr1(i) <= unsigned(drvRowCntr1(i)) - 1 ;
						end if ;
					end loop ;
				end if ;
			end if ;
		end if ;
	end process ;

	-- drvRows
	drvRowGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			drvRow0 <= (others => '0') ;
			drvRow1 <= (others => '0') ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				drvRow0 <= (others => '0') ;
				drvRow1 <= (others => '0') ;
			else
				if (DivCntrZERO = '1' and preLoad_drvRow = '1') or
				   (DivCKE = '1' and cBlnk = '0') then
					for i in 0 to 7 loop
						if drvRowCntr0(i) = "0000" then
							drvRow0(i) <= '0' ;
						else
							drvRow0(i) <= '1' ;
						end if ;
						if drvRowCntr1(i) = "0000" then
							drvRow1(i) <= '0' ;
						else
							drvRow1(i) <= '1' ;
						end if ;
					end loop ;
				end if ;
			end if ;
		end if ;
	end process ;

	-- preLoad drvRow enable
	prLdrvRowGen: process(CLK, nRST)
	begin
		if nRST = '0' then
			preLoad_drvRow <= '0' ;
		elsif rising_edge(CLK) then
			if nsyncRST = '0' then
				preLoad_drvRow <= '0' ;
			else
				if DivCKECntr = Col2Row then
					preLoad_drvRow <= '1' ;
				else
					preLoad_drvRow <= '0' ;
				end if ;
			end if ;
		end if ;
	end process ;



end RTL ;