pwmtes.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

use ieee.std_logic_arith.all ;

entity PWMTES is port (
	clkin	: in std_logic ; 	-- CLK IN
    ccnt	: in std_logic_vector(9 downto 0);		-- 10bit Capture Counter
	pwm_out	: out std_logic 	-- PWM OUT
	) ;
end PWMTES ;

architecture arch_PWMTES of PWMTES is

signal tcnt	: std_logic_vector(9 downto 0);		-- 10bit Timer Counter

begin

process(clkin,ccnt)
begin	
 	if (clkin'event and clkin='1') then
		if (tcnt < 999 ) then	-- 0-999 loop counter
			tcnt <= tcnt+1;
	   	else
			tcnt <= "0000000000";
		end if;
		if (tcnt < ccnt ) then	
			pwm_out	<='1';
		else
			pwm_out <='0';
		end if;
	end if;	
end process;
	
end arch_PWMTES;