loopcnt.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = LoopCnt.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Module Declaration
module LoopCnt	(		clk,
						rstn,
						state,
						ab,
						cnt
					);


    //	port declaration
	input						clk, rstn;
	input	[2:0]				state;
	input	[19:0]				ab;
	output	[31:0]				cnt;

    //	reg & wire declaration
	reg		[31:0]				cnt;

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
			cnt		<=	0;
		end
		else	begin
			if(( state == 3'b101 ) & ( ab == 20'hF_FFFF ))	begin
				cnt		<=	cnt + 1;
			end
			else	begin
				cnt		<=	cnt;
			end
		end
	end

endmodule