out_buffers.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = OUT_Buffers.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Module Declaration
module OUT_Buffers	(	clk,				//	Synchronous clock input
						rstn,				//	Negative reset input
						d,					//	Data input
						q					//	Data output
					);

	parameter	WIDTH	=	8;

    //	port declaration
	input						clk, rstn;
	input	[WIDTH-1:0]			d;
	output	[WIDTH-1:0]			q;


    //	reg & wire declaration
	reg		[WIDTH-1:0]			q;

	/*	------------	output declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin

		if( !rstn )	begin
		//	reset state
			q	<=	{WIDTH{1'b0}};
		end
		else	begin
		//	normal state
			q	<=	d;
		end

	end

endmodule