write_state.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = write_state.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Define Declaration
`define		MAIN_WRITE		3'b001
`define		IDLE			4'b0000
`define		CMD				4'b0001
`define		WAIT1			4'b0010
`define		WAIT2			4'b0011
`define		WAIT3			4'b0100
`define		WRITE1			4'b0101
`define		WRITE2			4'b0110
`define		WRITE3			4'b0111
`define		WRITE4			4'b1000

//	Module Declaration
module	write_state	(	clk,				//	Synchronous clock input
						rstn,				//	Negative reset input
						main_state,
						state
				);

    //	port declaration
	input						clk, rstn;
	input	[2:0]				main_state;

	output	[3:0]				state;

    //	reg & wire declaration
	reg		[3:0]				state;
	reg		[3:0]				next_state;

	/*	------------	State Machine Declaration	------------	*/
	//	State Register
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
		//	reset state
			state	<=	`IDLE;
		end
		else begin
		//	next_state
			state	<=	next_state;
		end
	end

	//	------------	State controller	------------
	always	@( state or main_state ) begin

		case( state )

			//	IDLE State
			`IDLE:		begin
							if( main_state == `MAIN_WRITE )	begin
							//	move next state
								next_state		<=	`CMD;
							end
							else	begin
							//	hold state
								next_state		<=	`IDLE;
							end
						end

			//	CMD State
			`CMD:		begin
							next_state		<=	`WAIT1;
						end

			//	WAIT1 State
			`WAIT1:		begin
							next_state		<=	`WAIT2;
						end

			//	WAIT2 State
			`WAIT2:		begin
							next_state		<=	`WAIT3;
						end

			//	WAIT3 State
			`WAIT3:		begin
							next_state		<=	`WRITE1;
						end

			//	WRITE1 State
			`WRITE1:	begin
							next_state		<=	`WRITE2;
						end

			//	WRITE2 State
			`WRITE2:	begin
							next_state		<=	`WRITE3;
						end

			//	WRITE3 State
			`WRITE3:	begin
							next_state		<=	`WRITE4;
						end

			//	WRITE4 State
			`WRITE4:	begin
							next_state		<=	`IDLE;
						end
						
			default:	begin
							next_state		<=	`IDLE;
						end
						
		endcase
	end

endmodule