io_buffers.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = IO_Buffers.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Module Declaration
module IO_Buffers	(	clk,				//	Synchronous clock input
						rstn,				//	Negative reset input
						enable,
						in,					//	
						q					//	Data output
					);

    //	port declaration
	input					clk, rstn;
	input					enable;
	input	[35:0]			in;
	output	[35:0]			q;


    //	reg & wire declaration
	reg		[35:0]			q;
	reg						enb;
	
	/*	------------	output-enable declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin

		if( !rstn )	begin
		//	reset state
			enb		<=	1'b0;
		end
		else	begin
			enb		<=	enable;
		end
	end

	/*	------------	output declaration		------------	*/
	always	@( posedge clk or negedge rstn )	begin

		if( !rstn )	begin
		//	reset state
			q	<=	36'hz_zzzz_zzzz;
		end
		else	begin
			if( enb )	begin
				q	<=	in;
			end
			else	begin
				q	<=	36'hz_zzzz_zzzz;
			end
		end
	end

endmodule