delay.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = Delay.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Module Declaration
module Delay	(		clk,
						rstn,
						start
					);


    //	port declaration
	input						clk, rstn;
	output						start;

    //	reg & wire declaration
	reg		[15:0]				cnt;

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn )	begin
			cnt	<=	16'h0;
		end
		else	begin
			if( cnt == 16'hffff )	begin
				cnt		<=	cnt;
			end
			else	begin
				cnt		<=	cnt + 1'b1;
			end
		end
	end

	assign	start	=	( cnt == 16'hffff );
endmodule