read_state.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------

	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = read_state.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Define Declaration

//	Module Declaration
module	read_state	(	clk,				//	Synchronous clock input
						rstn,				//	Negative reset input
						main_state,
						state
				);

	parameter		MAIN_READ	=	3'b010;

	parameter		IDLE		=	4'b0000;
	parameter		CMD			=	4'b0001;
	parameter		WAIT1		=	4'b0010;
	parameter		WAIT2		=	4'b0011;
	parameter		WAIT3		=	4'b0100;
	parameter		WAIT4		=	4'b0101;
	parameter		READ1		=	4'b0110;
	parameter		READ2		=	4'b0111;
	parameter		READ3		=	4'b1000;
	parameter		READ4		=	4'b1001;

    //	port declaration
	input						clk, rstn;
	input	[2:0]				main_state;

	output	[3:0]				state;

    //	reg & wire declaration
	reg		[3:0]				state;
	reg		[3:0]				next_state;

	/*	------------	State Machine Declaration	------------	*/
	//	State Register
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
		//	reset state
			state	<=	IDLE;
		end
		else begin
		//	next_state
			state	<=	next_state;
		end
	end

	//	------------	State controller	------------
	always	@( state or main_state ) begin

		case( state )

			//	IDLE State
			IDLE:		begin
							if( main_state == MAIN_READ )	begin
							//	move next state
								next_state		<=	CMD;
							end
							else	begin
							//	hold state
								next_state		<=	IDLE;
							end
						end

			//	CMD State
			CMD:		begin
							next_state		<=	WAIT1;
						end

			//	WAIT1 State
			WAIT1:		begin
							next_state		<=	WAIT2;
						end

			//	WAIT2 State
			WAIT2:		begin
							next_state		<=	WAIT3;
						end

			//	WAIT3 State
			WAIT3:		begin
							next_state		<=	WAIT4;
						end

			//	WAIT4 State
			WAIT4:		begin
							next_state		<=	READ1;
						end

			//	READ1 State
			READ1:		begin
							next_state		<=	READ2;
						end

			//	READ2 State
			READ2:		begin
							next_state		<=	READ3;
						end

			//	READ3 State
			READ3:		begin
							next_state		<=	READ4;
						end

			//	READ4 State
			READ4:		begin
							next_state		<=	IDLE;
						end

			default:		begin
							next_state		<=	IDLE;
						end
		endcase
	end

endmodule