main_state.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------

	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = main_state.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Define Declaration

//	Module Declaration
module	main_state	(	clk,				//	Synchronous clock input
						rstn,				//	Negative reset input
						start,

						state,
						write_state,
						read_state,
						
						cmp1_buf,
						cmp2_buf,
						cmp3_buf,
						cmp4_buf
				);

	parameter	IDLE			=	3'b000;
	parameter	WRITE			=	3'b001;
	parameter	READ			=	3'b010;
	parameter	COMP_WAIT		=	3'b011;
	parameter	COMP			=	3'b100;
	parameter	INC				=	3'b101;
	parameter	BAD				=	3'b110;
	parameter	WRITE_WRITE4	=	4'b1000;
	parameter	READ_READ4		=	4'b1001;

    //	port declaration
	input						clk, rstn;
	input						start;

	output	[2:0]				state;
	input	[3:0]				write_state;
	input	[3:0]				read_state;

	input						cmp1_buf;
	input						cmp2_buf;
	input						cmp3_buf;
	input						cmp4_buf;
	
    //	reg & wire declaration
	reg		[2:0]				state;
	reg		[2:0]				next_state;

	/*	------------	State Machine Declaration	------------	*/
	//	State Register
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
		//	reset state
			state	<=	IDLE;
		end
		else begin
		//	next_state
			state	<=	next_state;
		end
	end

	//	------------	State controller	------------
	always	@( state or start or write_state or read_state or cmp1_buf or cmp2_buf or cmp3_buf or cmp4_buf ) begin

		case( state )

			//	IDLE State
			IDLE:		begin
							if( start )	begin
							//	move next state
								next_state		<=	WRITE;
							end
							else	begin
							//	hold state
								next_state		<=	IDLE;
							end
						end

			//	WRITE State
			WRITE:		begin
							if( write_state == WRITE_WRITE4 )	begin
							//	move next state
								next_state		<=	READ;
							end
							else	begin
							//	hold state
								next_state		<=	WRITE;
							end
						end

			//	READ State
			READ:		begin
							if( read_state == READ_READ4 )	begin
							//	move next state
								next_state		<=	COMP_WAIT;
							end
							else	begin
							//	hold state
								next_state		<=	READ;
							end
						end

			//	COMP_WAIT State
			COMP_WAIT:	begin
							next_state		<=	COMP;
						end

			//	COMP State
			COMP:		begin
							if( cmp1_buf & cmp2_buf & cmp3_buf & cmp4_buf )	begin
								next_state		<=	INC;
							end
							else	begin
								next_state		<=	BAD;
							end
						end

			//	INC State
			INC:		begin
							next_state		<=	WRITE;
						end

			//	BAD State
			BAD:		begin
							next_state		<=	BAD;
						end
						
			default:	begin
							next_state		<=	BAD;
						end
		endcase
	end

endmodule