ssram.v

DesignWave 2005 8 Verilog Example

/* -------------------------------------------------------------
	Synthesis & Fitter tool = "QuartusII5.0WE"

	FileName = SSRAM.v

	M.YOSHIDA				15.MAY.2005		REV	1.0
------------------------------------------------------------- */
//	Module Declaration
module	SSRAM	(	clk,
					rstn,
					start,
					lfsr,

					write_enable,					
					ssram_q,
					ab,
					csn,
					wn,
					gn,
					bwan,
					bwbn,
					bwcn,
					bwdn,
					adv,
					cken,
					
					main_state,
					count
				);

	parameter		MAIN_IDLE		=	3'b000;
	parameter		MAIN_WRITE		=	3'b001;
	parameter		MAIN_READ		=	3'b010;
	parameter		MAIN_COMP_WAIT	=	3'b011;
	parameter		MAIN_COMP		=	3'b100;
	parameter		MAIN_INC		=	3'b101;
	parameter		MAIN_BAD		=	3'b110;

	parameter		WRITE_IDLE		=	4'b0000;
	parameter		WRITE_CMD		=	4'b0001;
	parameter		WRITE_WAIT1		=	4'b0010;
	parameter		WRITE_WAIT2		=	4'b0011;
	parameter		WRITE_WAIT3		=	4'b0100;
	parameter		WRITE_WRITE1	=	4'b0101;
	parameter		WRITE_WRITE2	=	4'b0110;
	parameter		WRITE_WRITE3	=	4'b0111;
	parameter		WRITE_WRITE4	=	4'b1000;

	parameter		READ_IDLE		=	4'b0000;
	parameter		READ_CMD		=	4'b0001;
	parameter		READ_WAIT1		=	4'b0010;
	parameter		READ_WAIT2		=	4'b0011;
	parameter		READ_WAIT3		=	4'b0100;
	parameter		READ_WAIT4		=	4'b0101;
	parameter		READ_READ1		=	4'b0110;
	parameter		READ_READ2		=	4'b0111;
	parameter		READ_READ3		=	4'b1000;
	parameter		READ_READ4		=	4'b1001;

    //	port declaration
	input						clk, rstn;
	input						start;
	input	[35:0]				lfsr;
	
	output						write_enable;
	input	[35:0]				ssram_q;
	output	[19:0]				ab;
	output						csn;
	output						wn;
	output						gn;
	output						bwan;
	output						bwbn;
	output						bwcn;
	output						bwdn;
	output						adv;
	output						cken;

	output	[2:0]				main_state;
	output	[7:0]				count;
	
    //	reg & wire declaration
	reg		[19:0]				ab;
	reg		[35:0]				db;
	reg							csn;
	reg							wn;
	reg							gn;
	reg							bwan;
	reg							bwbn;
	reg							bwcn;
	reg							bwdn;
	reg							adv;

	reg		[35:0]				write1_buf;
	reg		[35:0]				write2_buf;
	reg		[35:0]				write3_buf;
	reg		[35:0]				write4_buf;
	reg		[35:0]				read1_buf;
	reg		[35:0]				read2_buf;
	reg		[35:0]				read3_buf;
	reg		[35:0]				read4_buf;
	reg							cmp1_buf;
	reg							cmp2_buf;
	reg							cmp3_buf;
	reg							cmp4_buf;
	wire	[35:0]				ssram_q;
	
	wire	[2:0]				main_state;
	wire	[3:0]				write_state;
	wire	[3:0]				read_state;

	wire						write_enable;
	wire						byte_enable;
	wire						gn_enable;
	wire						wn_enable;
	wire						write_adv_enable;
	wire						read_adv_enable;
	wire	[35:0]				lfsr;

	reg		[7:0]				count;
	
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			ab[19:0]	<=	20'h0;
		end
		else begin
			if( main_state == MAIN_INC )	begin
				ab[19:0]	<=	ab[19:0] + 1'b1;
			end
			else	begin
				ab[19:0]	<=	ab[19:0];
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			db	<=	0;
		end
		else begin
			if( main_state == MAIN_INC )	begin
				db	<=	db + 1;
			end
			else	begin
				db	<=	db;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			csn	<=	1'b1;
		end
		else begin
			if(( write_state == WRITE_CMD ) | ( read_state == READ_CMD ))   begin
				csn	<=	1'b0;
			end
			else	begin
				csn	<=	1'b1;
			end
		end
	end

	assign	wn_enable	=	(( write_state == WRITE_CMD ) | ( write_state == WRITE_WAIT1 ) | ( write_state == WRITE_WAIT2 ) | ( write_state == WRITE_WAIT3 ));
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			wn	<=	1'b1;
		end
		else begin
			if( wn_enable )	begin
				wn	<=	1'b0;
			end
			else	begin
				wn	<=	1'b1;
			end
		end
	end

	assign	gn_enable	=	(( read_state == READ_CMD ) | ( read_state == READ_WAIT1 ) | ( read_state == READ_WAIT2 ) | ( read_state == READ_WAIT3 ) | ( read_state == READ_WAIT4 ) | ( read_state == READ_READ1 ));
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			gn	<=	1'b1;
		end
		else begin
			if( gn_enable )	begin
				gn	<=	1'b0;
			end
			else	begin
				gn	<=	1'b1;
			end
		end
	end

	assign	byte_enable	=	(( write_state == WRITE_CMD ) | ( write_state == WRITE_WAIT1 ) | ( write_state == WRITE_WAIT2 ) | ( write_state == WRITE_WAIT3 ));
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			bwan	<=	1'b1;
			bwbn	<=	1'b1;
			bwcn	<=	1'b1;
			bwdn	<=	1'b1;
		end
		else begin
			if( byte_enable )	begin
				bwan	<=	1'b0;
				bwbn	<=	1'b0;
				bwcn	<=	1'b0;
				bwdn	<=	1'b0;
			end
			else	begin
				bwan	<=	1'b1;
				bwbn	<=	1'b1;
				bwcn	<=	1'b1;
				bwdn	<=	1'b1;
			end
		end
	end

	assign	write_adv_enable	=	(( write_state == WRITE_WAIT1 ) | ( write_state == WRITE_WAIT2 ) | ( write_state == WRITE_WAIT3 ));// | ( write_state == WRITE_WRITE1 ));
	assign	read_adv_enable		=	(( read_state == READ_WAIT1 ) | ( read_state == READ_WAIT2 ) | ( read_state == READ_WAIT3 ));
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			adv	<=	1'b0;
		end
		else begin
			if( write_adv_enable | read_adv_enable )	begin
				adv	<=	1'b1;
			end
			else	begin
				adv	<=	1'b0;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			write1_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( write_state == WRITE_WAIT3 )	begin
				write1_buf	<=	lfsr;
			end
			else	begin
				write1_buf	<=	write1_buf;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			write2_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( write_state == WRITE_WRITE1 )	begin
				write2_buf	<=	lfsr;
			end
			else	begin
				write2_buf	<=	write2_buf;
			end
		end
	end
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			write3_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( write_state == WRITE_WRITE2 )	begin
				write3_buf	<=	lfsr;
			end
			else	begin
				write3_buf	<=	write3_buf;
			end
		end
	end
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			write4_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( write_state == WRITE_WRITE3 )	begin
				write4_buf	<=	lfsr;
			end
			else	begin
				write4_buf	<=	write4_buf;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			read1_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( read_state == READ_READ1 )	begin
				read1_buf	<=	ssram_q;
			end
			else	begin
				read1_buf	<=	read1_buf;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			read2_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( read_state == READ_READ2 )	begin
				read2_buf	<=	ssram_q;
			end
			else	begin
				read2_buf	<=	read2_buf;
			end
		end
	end
	
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			read3_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( read_state == READ_READ3 )	begin
				read3_buf	<=	ssram_q;
			end
			else	begin
				read3_buf	<=	read3_buf;
			end
		end
	end
	
	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			read4_buf	<=	36'h0_0000_0000;
		end
		else begin
			if( read_state == READ_READ4 )	begin
				read4_buf	<=	ssram_q;
			end
			else	begin
				read4_buf	<=	read4_buf;
			end
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			cmp1_buf	<=	1'b0;
			cmp2_buf	<=	1'b0;
			cmp3_buf	<=	1'b0;
			cmp4_buf	<=	1'b0;
		end
		else begin
			cmp1_buf	<=	( write1_buf == read1_buf );
			cmp2_buf	<=	( write2_buf == read2_buf );
			cmp3_buf	<=	( write3_buf == read3_buf );
			cmp4_buf	<=	( write4_buf == read4_buf );
		end
	end

	always	@( posedge clk or negedge rstn )	begin
		if( !rstn ) begin
			count	<=	8'h00;
		end
		else begin
			if(( main_state == MAIN_INC ) & ( ab == 20'b1111_11111111_11111111 ))	begin
				count	<=	count + 1'b1;
			end
			else	begin
				count	<=	count;
			end
		end
	end

	/*	--------	Main-Statemachine Declaration	--------	*/
	main_state			state0	(	.clk( clk ),
									.rstn( rstn ),
									.start( start ),
									.state( main_state ),
									.write_state( write_state ),
									.read_state( read_state ),
									.cmp1_buf( cmp1_buf ),									
									.cmp2_buf( cmp2_buf ),
									.cmp3_buf( cmp3_buf ),									
									.cmp4_buf( cmp4_buf )									
								);

	/*	--------	Write-Statemachine Declaration	--------	*/
	write_state			state1	(	.clk( clk ),
									.rstn( rstn ),
									.main_state( main_state ),
									.state( write_state )
								);

	/*	--------	Read-Statemachine Declaration	--------	*/
	read_state			state2	(	.clk( clk ),
									.rstn( rstn ),
									.main_state( main_state ),
									.state( read_state )
								);

	assign	write_enable	=	(( write_state == WRITE_WAIT2 ) | ( write_state == WRITE_WAIT3 ) | ( write_state == WRITE_WRITE1 ) | ( write_state == WRITE_WRITE2 ));
	assign	cken			=	1'b0;

endmodule