led.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led is
  Port ( 
	  clk       : in  std_logic;										-- Clock
    rstn      : in  std_logic;										-- /Reset (Active Low)
    led1_data : in  std_logic_vector(7 downto 0); -- LED1 Data
    led2_data : in  std_logic_vector(7 downto 0);	-- LED2 Data
    led3_data : in  std_logic_vector(7 downto 0);	-- LED3 Data
    led4_data : in  std_logic_vector(7 downto 0);	-- LED4 Data
    led_sel   : out std_logic_vector(3 downto 0);	-- LED_SEL
    led_data  : out std_logic_vector(7 downto 0));-- 7segment Data
end led;

architecture rtl of led is

signal led_sel_s : std_logic_vector(3 downto 0);

begin

-- 7 Segment LED Select --
u_led_sel_s : process (clk, rstn)
begin
  if (rstn='0') then
	  led_sel_s <= "0111";
  elsif (clk'event and clk='1') then
	  led_sel_s <= led_sel_s(2 downto 0) & led_sel_s(3);
  end if;
end process;

-- 7 Segment LED Select Output Signal --
u_led_sel : process (clk, rstn)
begin
  if (rstn='0') then
	  led_sel <= "1111";
  elsif (clk'event and clk='1') then
	  led_sel <= led_sel_s;
  end if;
end process;

-- 7 Segment LED Data Output Signal --
u_led_datag : process (clk, rstn)
begin
  if (rstn='0') then
	  led_data <= "00000000";
  elsif (clk'event and clk='1') then
    if    (led_sel_s(0)='0') then
  	  led_data <= led1_data;
    elsif (led_sel_s(1)='0') then
  	  led_data <= led2_data;
    elsif (led_sel_s(2)='0') then
  	  led_data <= led3_data;
    elsif (led_sel_s(3)='0') then
  	  led_data <= led4_data;
    else
		  led_data <= "00000000";
		end if;
  end if;
end process;

end rtl;