hex2led_decoder.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hex2led_decoder is
  Port ( 
    clk       : in  std_logic;                    -- Clock
    rstn      : in  std_logic;                    -- /Reset (Active Low)
    hex_data  : in  std_logic_vector(3 downto 0); -- HEX Data
    led_data  : out std_logic_vector(7 downto 0));-- 7segment Data
end hex2led_decoder;

architecture rtl of hex2led_decoder is

begin

--HEX-to-7segment decoder
-- segment encoding
--      0
--     ---  
--  5 |   | 1
--     ---   <- 6
--  4 |   | 2
--     ---   . 7
--      3      
   
u_led_data : process (rstn, clk)
begin
  if (rstn='0') then
    led_data <= "00000000";
  elsif (clk'event and clk='1') then
    case hex_data is
      when "0000" => led_data <= "00111111";  -- Chr 0
      when "0001" => led_data <= "00000110";  -- Chr 1
      when "0010" => led_data <= "01011011";  -- Chr 2
      when "0011" => led_data <= "01001111";  -- Chr 3
      when "0100" => led_data <= "01100110";  -- Chr 4
      when "0101" => led_data <= "01101101";  -- Chr 5
      when "0110" => led_data <= "01111101";  -- Chr 6
      when "0111" => led_data <= "00000111";  -- Chr 7
      when "1000" => led_data <= "01111111";  -- Chr 8
      when "1001" => led_data <= "01101111";  -- Chr 9
      when "1010" => led_data <= "01110111";  -- Chr A
      when "1011" => led_data <= "01111100";  -- Chr b
      when "1100" => led_data <= "00111001";  -- Chr C
      when "1101" => led_data <= "01011110";  -- Chr d
      when "1110" => led_data <= "01111001";  -- Chr E
      when "1111" => led_data <= "01110001";  -- Chr F
      when others => led_data <= "00000000";  -- not light
    end case;
  end if;
end process; 

end rtl;