chattering.vhd

DesignWave 2005 8 Verilog Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity chattering is
  Port (
    clk          : in  std_logic;
    rstn         : in  std_logic;
    sw_pulse_in  : in  std_logic;
    sw_pulse_out : out std_logic);
end chattering;

architecture rtl of chattering is

constant cha_cnt_max : integer := 1023;
signal chatter_hi_cnt : integer range 0 to cha_cnt_max; -- Hi  Counter
signal chatter_low_cnt : integer range 0 to cha_cnt_max; -- Low Counter
signal sw_pulse_out_tmp : std_logic;

begin

u_chatter_hi_cnt : process (rstn, clk)
begin
  if (rstn='0') then
    chatter_hi_cnt <= 0;
  elsif (clk'event and clk='1') then
    if (sw_pulse_in='1') then
      if (chatter_hi_cnt=cha_cnt_max) then
        chatter_hi_cnt <= chatter_hi_cnt;
      else
        chatter_hi_cnt <= chatter_hi_cnt + 1;
      end if;
    else
      chatter_hi_cnt <= 0;
    end if;
  end if;
end process;

u_chatter_low_cnt : process (rstn, clk)
begin
  if (rstn='0') then
    chatter_low_cnt <= 0;
  elsif (clk'event and clk='1') then
    if (sw_pulse_in='0') then
      if (chatter_low_cnt=cha_cnt_max) then
        chatter_low_cnt <= chatter_low_cnt;
      else
        chatter_low_cnt <= chatter_low_cnt + 1;
      end if;
    else
      chatter_low_cnt <= 0;
    end if;
  end if;
end process;

u_sw_pulse_out_tmp : process (rstn, clk)
begin
  if (rstn='0') then
    sw_pulse_out_tmp <= '0';
  elsif (clk'event and clk='1') then
    if (chatter_hi_cnt=cha_cnt_max) then
      sw_pulse_out_tmp <= '1';
    elsif (chatter_low_cnt=cha_cnt_max) then
      sw_pulse_out_tmp <= '0';
    else
      sw_pulse_out_tmp <= sw_pulse_out_tmp;
    end if;
  end if;
end process;

u_sw_pulse_out : sw_pulse_out <= sw_pulse_out_tmp;

end rtl;